How To Reference Input pins to Cells

[Altera_Forum]

I need to reference a pin which goes into the clock pin of a cell I have created. I have used the Net Finder within timequest yet I am still unable to reference this pin. I have been able to use the Net Finder to aid in refencing i/o ports and pll clock pins so it is just the input pin to this cell that is giving me problems. 

 Here is my situation: I have a clock mux controlled by hardware outside of the fpga. The output of the clock mux goes to a single input pin to the fpga (clock A, clock B). I have created SDC constraints for muxed clocks, clock A and clock B. This single input clock pin is connected to two cells (cell A, cell B). Cell A uses clock A and cell B uses clock B. I need to create a false path from clock A to Cell B and vice versa. Therefore I need to reference the input clock pins to each of these cells.  I have tried using the following two SDC constraint but this did not create the false path I needed:  set_false_path   -from [get_clocks {pclk_pin_a}]   -to [get_registers {*inst43*}]   set_false_path   -from [get_clocks {pclk_pin_a}]   -to [get_nodes {*inst43*}]     Am I doing this correctly? Is this how false paths are intended to be used? Is there a tutorial or information on how Timequest / tcl references pins?

[Altera_Forum]

When you state it's not creating the false path you need, why not? What path shows up that wasn't cut by this? 

A path being analyzed tends to have four features, a launch clock, a latch clock, a from node and a to node. The set_false_path has options to filter paths based on these paths. So the first statement above will cut any path where pclk_pin_a is the launch clock and *inst43* matches the latch clock. I believe these types of paths won't show up, and so it's something else you're seeing being analyzed to say it's not doing what you need.