How to dump the netlist in Verilog for reading the implementation done by Quartus

[Altera_Forum]

I just want to know ppl that is there a way by which we can see the compiled and synthesized netlist, I have come across only the netlist viewer tool in GUI which when I open in resource editor I cannot get any clue of the functionality of the blocks because it used signs like# ,$,^,! . 

I can take a guess for ^ &! but not others.  Is there anyother way around?

[Altera_Forum]

One option is to enable the *.vho netlist output for ModelSim gate level simulation. It gives a flat VHDL-like netlist.

[Altera_Forum]

--- Quote Start ---  I just want to know ppl that is there a way by which we can see the compiled and synthesized netlist...  --- Quote End ---     You can generate equations files at "Processing --> Start --> Start Equation Writer". You can get the equations for the state of the netlist at the end of synthesis and the state at the end of fitting.  I like to use the HTML version of the equations files so that it is easy to trace backward through the equations using hyperlinks. Enable generation of the HTML version at "Tools --> Options --> General --> Processing --> Automatically generate HTML-Format Report Files (.htm) after design processing". You can also generate the equations files automatically during every compilation using another checkbox in this dialog box.  If you want to see the equations for just a small part of the design, locate a node at that part of the design in the Chip Planner. Enable "View --> Equations". If you don't see the equations for the selected node(s) at the bottom of the Chip Planner window, drag up the pane separator from the bottom edge.  The equations will be written in terms of primitives. You need to know what each port is for the primitives. On the Index tab in Help, type "primitives" without the quotes. Go to the subtopic "viewing in equations".      --- Quote Start ---  I cannot get any clue of the functionality of the blocks because it used signs like# ,$,^,! . I can take a guess for ^ &! but not others.  --- Quote End ---    The Boolean symbols in the equations are the same as those for AHDL. On the Search tab in Help, enter "Logical Operators (AHDL)" with the quotes to get a table of the operator symbols.