How to properly set up a stratix 10 transceiver in Quartus 17.1

[SDe_J]

Hello,

I'm trying to implement an l-tile transceiver in Quartus 17.1.

I have implemented the transceiver with the PCS direct setting, as I have custom fpga code for decoding.

I have implemented the fPLL for the tx_clock. (I also tried the CMU pll)

I have implemented separate tx and rx resets

I have assigned the tx and rx pins to the appropriate qsfp pins

When I compile the project, I get this error:

Error(14566): The Fitter cannot place 2 periphery component(s) due to conflicts with existing constraints (2 I/O pad(s)). Fix the errors described in the submessages, and then rerun the Fitter. The Intel FPGA Knowledge Database may also contain articles with information on how to resolve this periphery placement failure. Review the errors and then visit the Knowledge Database at https://www.altera.com/support/support-resources/knowledge-base/search.html and search for this specific error message number. Error(175001): The Fitter cannot place 1 I/O pad. Info(14596): Information about the failing component(s): Info(175028): The I/O pad name(s): ser_rx(n) Error(16234): No legal location could be found out of 1 considered location(s). Reasons why each location could not be used are summarized below: Error(175001): The Fitter cannot place 1 I/O pad. Info(14596): Information about the failing component(s): Info(175028): The I/O pad name(s): ser_rx_emul(n) Error(16234): No legal location could be found out of 1 considered location(s). Reasons why each location could not be used are summarized below:

I think I'm missing some other assignments, but I don't know what they are. Can you point me in the right direction?

Thanks!

-Sam

[SDe_J]

Evidently the manual I looked at was for the wrong device. It turns out the pins I has assigned were not correct. I looked at an example design and was able to find the correct pins.