How to use Avalon-MM Master BFM?

[Altera_Forum]

Hello, all. 

 I want to use Avalon Verification IP Suite to check a Qsys custom componet, which have an Avalon salve interface and a Avalon conduit interface connecting a LSI.  I wrote this program to test if the custom component can give right response to the Avalon Master BFM.   //Console messaging level `define VERBOSITY VERBOSITY_INFO //BFM hierachy `define CLK_BFM top.tb.clock_source `define RST_BFM top.tb.reset_source `define MM_MASTER top.tb.avalon_mm_master `define CONDUIT_BFM top.tb.conduit_bfm module test_program(); import verbosity_pkg::*; import avalon_mm_pkg::*; event start_test; event end_test; //---------------------------------------------------------------------------------- // Set verbosity before the test starts // Qsys-generated testbench activates clock and reset BMFs //---------------------------------------------------------------------------------- initial begin set_verbosity(`VERBOSITY); // initialize BFMS `MM_MASTER.init(); end //---------------------------------------------------------------------------------- // Main test block //---------------------------------------------------------------------------------- initial begin // wait for reset inactive wait(`RST_BFM.reset == 1); -> start_test; end initial begin @ start_test; // start write access `MM_MASTER.set_command_request(REQ_WRITE); `MM_MASTER.set_command_address(16'h0); `MM_MASTER.set_command_idle(2,0); `MM_MASTER.set_command_init_latency(0); `MM_MASTER.set_command_data(32'h0,0); `MM_MASTER.push_command(); end endmodule   Although this program can be compiled by ModelSim with no error, but it seems the write access was not started.  Can you give me some hints or some examples about how to test custom components wit Avalon IP verification suite?  Regards, feng

[Altera_Forum]

--- Quote Start ---   i tried what you mentioned in your post# 24    --- Quote End ---    Why oh why can you not read!? Post# 24 refers to a question about getting things to work in Quartus 13.1.  You have indicated that you are using Quartus 11.1sp1 which is what the tutorial I linked to in# 39 was written using. Are you reading through the PDF linked to on the Wiki tutorial???  *JUST READ THE TUTORIAL*  Ignore any of the discussion in this thread, as it relates to Quartus 13.1.  If you install Quartus 13.1, then qsys_vip.zip will work fine.  Cheers, Dave

[Altera_Forum]

--- Quote Start ---  Why oh why can you not read!? Post# 24 refers to a question about getting things to work in Quartus 13.1.  You have indicated that you are using Quartus 11.1sp1 which is what the tutorial I linked to in# 39 was written using. Are you reading through the PDF linked to on the Wiki tutorial???  *JUST READ THE TUTORIAL*  Ignore any of the discussion in this thread, as it relates to Quartus 13.1.  If you install Quartus 13.1, then qsys_vip.zip will work fine.  Cheers, Dave  --- Quote End ---     yes , i am referring to the wiki tutorial and the error i am getting : # ** Error: c:/temp/altera_jtag_to_avalon_mm_tutorial/hdl/qsys_system/test/qsys_system_bfm_master_tb.sv(48): Could not find the package (verbosity_pkg). Design read will continue, but expect a cascade of errors after this failure. Furthermore if you experience a vopt-7 error immediately before this error then please check the package names or the library search paths on the command line.# ** Error: c:/temp/altera_jtag_to_avalon_mm_tutorial/hdl/qsys_system/test/qsys_system_bfm_master_tb.sv(49): Could not find the package (avalon_mm_pkg). Design read will continue, but expect a cascade of errors after this failure. Furthermore if you experience a vopt-7 error immediately before this error then please check the package names or the library search paths on the command line.# C:/altera/11.1/modelsim_ase/win32aloem/vlog failed. -L qsys_system_bfm_master# invalid command name "-L"  is at this step:  ModelSim> vlog -sv $TUTORIAL/hdl/qsys_system/test/qsys_system_bfm_master_tb.sv -L qsys_system_bfm_master   The zip file in the previous post was the one i that was generated by following the steps in the wiki tutorial .  Thanks!

[Altera_Forum]

You still have a problem with reading :( 

 Read the message in the console output    --- Quote Start ---   # invalid command name "-L"   --- Quote End ---    Try putting the command on ONE line ...    --- Quote Start ---   ModelSim> vlog -sv $TUTORIAL/hdl/qsys_system/test/qsys_system_bfm_master_tb.sv -L qsys_system_bfm_master   --- Quote End ---    Cheers, Dave

[Altera_Forum]

--- Quote Start ---  You still have a problem with reading :(  Read the message in the console output    Try putting the command on ONE line ...      Cheers, Dave  --- Quote End ---      Yes David ,thanks! :) I began thinking in a very complicated way from the beginning :(

[Altera_Forum]

--- Quote Start ---  Yes David ,thanks! :) I began thinking in a very complicated way from the beginning :(  --- Quote End ---   I'm glad to hear you got things working!  Cheers, Dave

[Altera_Forum]

Hello, please I have problem with ModelSim SE peformance. I use Modelsim SE, my mixed-language design has 2 instances of RapidIO megafunction (they are crossed rx0 <= tx1 and rx1 <= tx0) and my own VHDL component. This is configured and made RapidIO transaction by Avalon-MM Master BFM, generated in QSYS. I compiled all the design files (RapidIO megafunction files are .vo) and when I run simulation, the simulation time 3us takes 1second normal real time, and it is too long for me, because I need simulate about 1 second simulation time (it is cca 3.8 days)... My PC configuration is Win7 64bit, 8GB RAM, Corei7 3.4GHz, SSD hdd. Please can someone help me or give me advice, how to solve this problem? How to improve Modelsim performance?  

Thank you in advance.

[Altera_Forum]

--- Quote Start ---  Hello, please I have problem with ModelSim SE peformance. I use Modelsim SE, my mixed-language design has 2 instances of RapidIO megafunction (they are crossed rx0 <= tx1 and rx1 <= tx0) and my own VHDL component. This is configured and made RapidIO transaction by Avalon-MM Master BFM, generated in QSYS. I compiled all the design files (RapidIO megafunction files are .vo) and when I run simulation, the simulation time 3us takes 1second normal real time, and it is too long for me, because I need simulate about 1 second simulation time (it is cca 3.8 days)... My PC configuration is Win7 64bit, 8GB RAM, Corei7 3.4GHz, SSD hdd. Please can someone help me or give me advice, how to solve this problem? How to improve Modelsim performance?    --- Quote End ---    This question is not really related to this thread ... since you're mainly concerned about Modelsim-SE performance.  The problem is that your design contains transceivers. I was recently simulating a design with several 5Gbps transceiver links controlled using a UART-to-Avalon-MM bridge. It took forever to simulate, since the relative speed of the UART at 1Mbps relative to the 5Gbps transceiver results in many many simulation deltas ... in the end I simulated a few basic transactions, and then went to hardware for further testing. The simulation was performed using Modelsim-SE on a machine with 8 cores and 16GB RAM ...   So, my recommendation is, use simulation to check that you have no fundamental issues (no red in the simulation), and then test in hardware and use SignalTap II to trace any interesting details.  Cheers, Dave

[Altera_Forum]

Hi guys. 

I used "Altera JTAG-to-Avalon-MM Tutorial" to simulate My custom hardware which is like this: https://www.alteraforum.com/forum/attachment.php?attachmentid=10029  and the way i communicate with it last time in DE2 board through NIOS was like this:  #include<stdio.h> # include<unistd.h> # include "system.h" # include "alt_types.h" # include <io.h> # ifndef loadstart # define loadstart 0x0 # endif # ifndef loadnxt # define loadnxt 0x1 # endif # ifndef loadwe # define loadwe 0x2 # endif # ifndef loadeaddr # define loadeaddr 0x3 # endif # ifndef loadAi0 # define loadAi0 0x4 # endif # ifndef loadAi1 # define loadAi1 0x5 # endif # ifndef loadAi2 # define loadAi2 0x6 # endif # ifndef loadAi3 # define loadAi3 0x7 # endif # ifndef loadBi0 # define loadBi0 0x8 # endif # ifndef loadBi1 # define loadBi1 0x9 # endif # ifndef loadBi2 # define loadBi2 0xA # endif # ifndef loadBi3 # define loadBi3 0xB # endif # ifndef readsum # define readsum 0xC # endif # ifndef readpdone # define readpdone 0xD # endif # ifndef readdone # define readdone 0xE # endif void matrixmul(int A,int B,int C) { int k=0; IOWR(MATRIXMUL_0_BASE,loadwe,1); int i,l,m; for(i=0; i<16; i++) { int j=0; while(j<16) { IOWR(MATRIXMUL_0_BASE,loadeaddr,k); IOWR(MATRIXMUL_0_BASE, loadAi0, A); IOWR(MATRIXMUL_0_BASE, loadAi1, A); IOWR(MATRIXMUL_0_BASE, loadAi2, A); IOWR(MATRIXMUL_0_BASE, loadAi3, A);; IOWR(MATRIXMUL_0_BASE, loadBi0, B); IOWR(MATRIXMUL_0_BASE, loadBi1, B); IOWR(MATRIXMUL_0_BASE, loadBi2, B); IOWR(MATRIXMUL_0_BASE, loadBi3, B); ... But Now I dont know how to communicate with my custom hardware in testbench using "avalon_write" or "avalon_read" since I need to access this signals directly: input clk, reset; input chipselect; input [2:0] address; input write; input [31:0] writedata; output [31:0] readdata;  I would appreciate if somebody help me. regards

[Altera_Forum]

It looks like your component is an Avalon-MM slave. In that case, you can just create a Qsys system with an Avalon-MM master BFM and your component, and then simulate that. 

   --- Quote Start ---   I dont know how to communicate with my custom hardware in testbench using "avalon_write" or "avalon_read" since I need to access this signals directly   --- Quote End ---   You do not need to access those signals. The Avalon-MM master BFM would generate the transaction over the Avalon-MM bus.  All you need to write is a testbench with avalon_read and avalon_write commands that match your NIOS II code.  Cheers, Dave

[Altera_Forum]

Hi Dave, 

I need information about burst write operation in avalon bfm. Below i mentioned the task which i am using. In that burst_size is 3 and burst_count in each burst is 2.So totally 6 data transaction will happen.But In my case i am getting only three data transacation and and address is also not incrementing(Adress is zero for all transaction).  Please help me ... I am new to protocol..   ////////////////////////////////Task //////////////////////////////////////  task data_init(output bit[511:0] data [int]); for(int i=0; i<6; i++) data = {$random(), $random()}; endtask  task avalon_write ([34:0] addr, bit[511:0] data [int]); // construct the bfm request `bfm.set_command_request(req_write); `bfm.set_command_idle(0, 0); `bfm.set_command_init_latency(0); `bfm.set_command_address(addr);  `bfm.set_command_burst_size(3); `bfm.set_command_burst_count(2);  for(int i=0; i<6; i++) begin `bfm.set_command_data(data, i); `BFM.set_command_byte_enable(48'hffff_ffff_ffff,i) ; end // Queue the command `BFM.push_command();  // Wait until the transaction has completed while (`BFM.get_response_queue_size() != 1) @(posedge `BFM.clk);  // Dequeue the response and discard `BFM.pop_response(); endtask  bit[511:0] wdata[int]; /////////////////////////////  initial begin data_init(wdata); avalon_write('d0,wdata); end ///////////////////////////////   Thanks Venkat