How to use multiple sdc files?

[Altera_Forum]

In Settings for TimeQuest Timing Analyzer, we can add several sdc files into it. I just wonder in which case we should use multiple sdc files? 

 If in my design, there are several sub modules, can I write sdc file for each module? If I can, how TimeQuest know which sdc file should match with the corresponding module?  Thanks very much.

[Altera_Forum]

In case of really large project that span months of team work you may prefer to have a main project sdc file that can call some lower sdc files that contain constraints specific to nodes in lower modules. You will put clock, pins etc in top level and local constraints such as multicycles or delays in lower level sdc files then call them up from top sdc using: 

 read_sdc sdc1.sdc read_sdc sdc2.sdc  This is convenient for team work when a designer of lower module passes constraints to project level integrator.

[Altera_Forum]

You could have a look to ALTERA design kits. 

Some contains cascade of sdc scripts. For example that one : http://www.altera.com/products/devkits/altera/kit-stratix-v-gx-100g.html with multiple scripts of Ethernet RGMII constraints called in order by a top level sdc.

[Altera_Forum]

--- Quote Start ---  In case of really large project that span months of team work you may prefer to have a main project sdc file that can call some lower sdc files that contain constraints specific to nodes in lower modules. You will put clock, pins etc in top level and local constraints such as multicycles or delays in lower level sdc files then call them up from top sdc using:  read_sdc sdc1.sdc read_sdc sdc2.sdc  This is convenient for team work when a designer of lower module passes constraints to project level integrator.  --- Quote End ---    Thanks, kaz. But I am still a little confused about how to allocate constraints in each sdc file. I think I should read some example design with multiple sdc files.  Just take example, if I have a top design "T", inside this top design, there are several modules "a", "b, "c". Is that possible I write sdc file "a.sdc", "b.sdc", "c.sdc" for each of them, and read all of them in "T.sdc"?  Thanks very much.

[Altera_Forum]

It is quite simple convenience, nothing technical. 

You design a module named buddha_fft.vhd. You will use your full sdc file called buddha_fft.sdc that declares system clocks,multicycles,false paths but you don't care about io. Once finished, you send your design to project integrator. He/She will read your sdc file and know any local constraints. Will convert them to project level names and add them to his/her sdc but may be more organized and put them in a separate sdc called buddha_fft.sdc after removing your project level constraints and editing node names.   I don't know about other applications of multiple sdc files. I may have several files to see which is better but will need to set project to one of them for a given build.

[Altera_Forum]

--- Quote Start ---  It is quite simple convenience, nothing technical. You design a module named buddha_fft.vhd. You will use your full sdc file called buddha_fft.sdc that declares system clocks,multicycles,false paths but you don't care about io. Once finished, you send your design to project integrator. He/She will read your sdc file and know any local constraints. Will convert them to project level names and add them to his/her sdc but may be more organized and put them in a separate sdc called buddha_fft.sdc after removing your project level constraints and editing node names.   I don't know about other applications of multiple sdc files. I may have several files to see which is better but will need to set project to one of them for a given build.  --- Quote End ---    Thanks very much, kaz. Your post remind me an issue that TimeQuest will assign the same name sdc file to same name design file as default. I remember it is like if I have a design file  "buddha_fft.vhd", then it will match with "buddha_fft.sdc" as default, if there is no "buddha_fft.sdc", TimeQuest will try to use others.