Internally connect exported bus.

[Altera_Forum]

Hello. I want to split my qsys design into 2 parts: the A is Nios processor and some peripherials, and B is dsp. They both have to use sdram so the plan is to connect it in the top level system through pipeline bridge. The problem i've faced is i can not export data_master and instruction_master outlets unless it breaks internal connections. Any way to bypass this?

[Altera_Forum]

Do you want to connect A and B outside of Qsys? Why don't you use hierarchy in QSys by designing two sub systems and connecting them together in a top level QSys design? Connecting them outside of QSys is very difficult and can lead to problems with memory mapping. 

If you use two sub systems in a top level QSys project there shouldn't be any problem connecting pipeline bridges together.

[Altera_Forum]

--- Quote Start ---  Why don't you use hierarchy in QSys by designing two sub systems and connecting them together in a top level QSys design?  --- Quote End ---   That is exactly what i want to do :) My top level qsys system should include subsystem A, subsystem B and sdram controller, connected to both through bridge. But I don't know how to export avalon mm bus without loosing internal connections.

[Altera_Forum]

Can you show a screenshot of your subsystems? 

In the A subsystem, you should add a pipeline bridge, and connect the Nios' instruction and data masters to the pipeline bridge slave input. If you have DMAs that also need access to the SDRAM, connect them too to the pipeline bridge slave. Then on the pipeline bridge, define the master interface as an export. Do the same thing on the subsystem B. Then when you add both subsystems to the top level QSys design, both should appear with an Avalon master interface, and you can connect both to the SDRAM.