LVDS is input only in CycIII? no way!

[Altera_Forum]

I just received the following error message from QuartusII using a CycIII for LVDS outputs. The errored pins are in bank 4. 

 "Error: I/O standard LVDS on output or bidirectional pin DAC_data1p is illegal -- I/O standard only allowed on input pins"   Anyone know why this is happening?  Thank you in advance, BR

[Altera_Forum]

In general, LVDS is allowed for both inputs and outputs. Maybe there is a Cyclone III restriction for the particular side of the device you are using. (In some device families, pins on the top/bottom sides have LVDS support different from that on the left/right sides.) 

 Right-click the error message and go to its Help page to see if you get any clues there.   Later update: The Help page doesn't add much information for this error. You would have to use the device handbook to find out that the reason for the error is what FvM said in his post below about my suggestion that the restriction is related to the side of the device.

[Altera_Forum]

For Cyclone III top and bottom banks, LVDS output is supported with resistor divider only, the setting is LVDS_E_3R in pin planner.

[Altera_Forum]

Thank you, FvM, that worked. Now, I just need to figure out where to get all of those resistors from.

[Altera_Forum]

For lower data rates, also the RSDS_E_1R one resistor solution may be used.

[Altera_Forum]

Digikey, Arrow or Future will gladly sell you the resistors.