MegaWizard Altsyncram generated component uses more M4K blocks then reported

[Altera_Forum]

I have the following MegaWizard generated component: 

SUBDESIGN ipdram (  clock : INPUT;  data[23..0] : INPUT;  rdaddress[9..0] : INPUT;  wraddress[9..0] : INPUT;  wren : INPUT = VCC;  q[23..0] : OUTPUT; )  VARIABLE   altsyncram_component : altsyncram WITH (  ADDRESS_REG_B = "CLOCK0",  CLOCK_ENABLE_INPUT_A = "BYPASS",  CLOCK_ENABLE_INPUT_B = "BYPASS",  CLOCK_ENABLE_OUTPUT_A = "BYPASS",  CLOCK_ENABLE_OUTPUT_B = "BYPASS",  INTENDED_DEVICE_FAMILY = "Cyclone II",  LPM_TYPE = "altsyncram",  MAXIMUM_DEPTH = 512,  NUMWORDS_A = 680,  NUMWORDS_B = 680,  OPERATION_MODE = "DUAL_PORT",  OUTDATA_ACLR_B = "NONE",  OUTDATA_REG_B = "UNREGISTERED",  POWER_UP_UNINITIALIZED = "FALSE",  READ_DURING_WRITE_MODE_MIXED_PORTS = "DONT_CARE",  WIDTHAD_A = 10,  WIDTHAD_B = 10,  WIDTH_A = 24,  WIDTH_B = 24,  WIDTH_BYTEENA_A = 1  );  The MegaWizard reports a usage of 4 M4K blocks and some Luts for this component. However when I instantiate the generated component in my design, the fitter uses 5 M4K blocks. I am one M4K block short in my total design, the one block less for the 4 instantiations I have would save my day!

[Altera_Forum]

Your max depth is 512, making a 512x9 RAM, which I thought would actually use 6. At 640x24, I'm not quite sure how it would be done with 4 M4Ks. Your width and deptch aren't nice powers of 2, and you end up wasting bits in both directions. If you can't reduce the depth a little, maybe you have open registers in the design that could be used to build out the last M4K?

[Altera_Forum]

Let's leave the binary boundaries aside for a momemt. Life isn't always that simple ... 

Actually in x9 mode, it 4 M4K should hold 768 24 bit words.  The question was: why does the fitter use 5 M4K if the MegaWizard reports it can do it in 4? I the depth is limited to 256, the MegaWizard also reports 4 M4K used but about 50 Lut in stead of about 20 for the depth of 512. If we leave it Auto, it will use 6 M4K (in 2048 x 2).   By the way: the design is 106% full (after Analysis and Synthesis). I already have a few logic-Cells based dcfifo I'd like to replace with the free M4K blocks.

[Altera_Forum]

I see what you're saying. I would just do it by hand. Make a 512x24 RAM, which should use 3 M4Ks, and make a 128x24 RAM, which should use 1, and use your MSB address to select.

[Altera_Forum]

What do we have the Megawizard for then? 

 512 x 24 and 128 x 24 don't give me 680 by 24 yet. The megawizard handles the 640 * 24 as you say, if we limit the depth to 256 or 512, but if you use it that way, the fitter still takes 5 M4K. I'll maybe put in a support request, but in the mean time work my way around it.

[Altera_Forum]

So I'm really confused. What version of the tools are you using? I just ran through the megawizard using the same configuration you are using for the RAM and the megawizard is reporting a usage of 6 M4K blocks for me. 

 Jake

[Altera_Forum]

Quartus II version 9.0 Build 132 02/25/2009 SJ Full Version 

 Service Pack Installed: None Help Version: Quartus II Help Version 9.0  I was aiming at: 680 words of 24 bits in dual-port - single clock mode without registering the output data (maybe forcing it to use M4K blocks) while limiting the depth to either 256 or 512  I'll attach the .tdf of the generated function.

[Altera_Forum]

If you set the max block depth 512 then the megawizard will report resource usage of 25 lut + 4 M4K + 2 reg.  

I've no idea why this wouldn't be true in the fitter results however.

[Altera_Forum]

The Megawizard isn't overly smart. I believe it makes all the rams 512 deep and then stitches them together. This simple methodology works 99% of the time as most RAMs are close to powers of 2. Yes, it could be smarter, but it's a lot better than the old days at X where you had to stitch every single RAM out of RAM primitives. If I have to do it once in a while, it usually take a few minutes and that's it. (But file a request with Altera, as there's no reason it couldn't do this...)