Neuron implementation in VHDL (code attached)

[Altera_Forum]

Hi all.I am just learning VHDL and as an exercise, I am trying to model a neuron in VHDL (attached the code). The neuron has three inputs, three weights and one threshold value (as entity inputs).The neuron is selected through the enableIN and if it is set as '1' ,the neuron reads the inputs, weights and threshold.After that, I created three process for calculate a product between inputs and weights, a sum of these products and at the end a sigmoid function of that summation.What I would like to know is if I wrote these data-flow and behavioral models inside the entity as It is expected to work.The objective is the output having the result of the function when enableOUT is set '1'.I appreciate any help, thanks.

[Altera_Forum]

Don't be too crusty... I am doing my best. 

 In this case, I need to use the neuron.vhdl with the modelsim, not the LATANN_top.vhdl generated with the bdf design file. Because with the design file, the "internal signals" are not shown in modelsim.   I'll try it now, and show the results.

[Altera_Forum]

Yes, 

 the clock is connected in pin 8. Let me try to simulate with the neuron.vhdl and see what is happened inside the component.

[Altera_Forum]

I simulated via LATANN_top.vhd instantiated inside my own testbench and it ran just fine, until it freezes in the OUT_state.

[Altera_Forum]

Did you write some testbench? Didn't you use the modelsim (create wave)? 

 What time interval did you use? Default one (mine is 1000 ps). What time the results were achieved (output and out_en)?  Thanks :D

[Altera_Forum]

Do I need to insert all vhdl files other than just LATANN_top.vhdl file in the ModelSim Project before compile and simulate (all in modelSim)?  

I mean, neuron.vhdl, fixed_float_types_c.vhdl and fixed_pkg_c.vhdl ?

[Altera_Forum]

you dont need any project. You can compile the code yourself. The fixed_pkg is part of the IEEE library, so you may need to edit your code a little to reflect this, but you can compile with: 

 vcom neuron.vhdl -2008 vcom LATANN_top.vhdl vcom your_vhdl_testbench.vhd  vsim your_vhdl_testbench  run 1us (or however long you want the sim to run for)  I made a 10ns clock in my quick testbench. I didnt crete waveforms, I just created a clock, reset in VHDL and connected all the inputs to "0000000001", and enable to 1.

[Altera_Forum]

After creating a new project in ModelSim Altera, in a new folder.  

I created a library called ieee_proposedfor the two imported files (fixed_pkg_c.vhdl fixed_float_types_c.vhdl) used withmy vhdl files (neuron.vhdl).   The steps to create the library ieee_proposed is as follow: vlib ieee_proposed vmap ieee_proposed ./ieee_proposed vcom -work ieee_proposed ./fixed_pkg_c.vhdl ./fixed_float_types_c.vhdl  Then, after importing the vhdl files to my project, I used the "Order option" to solve the dependencies in compilation. I compiled.  The simulation occurs normaly, but the output always goes to "0000000001".  Compilation results in modelsim: http://puu.sh/6jti0/b1b1dcd9c3.png  ModelSim: simulation: http://puu.sh/6juh2/e8e0c8cf9d.png  Until here, in resume, all the problem was due to the compilation using the modelSim (I didnt know how to do it).  Now I will try to solve the "output="0000000001" going ever" problem :D.  Thank you very much Tricky.  I will post my results.