New component in SOPC Builder 9.0

[Altera_Forum]

I switched to Quartus 9.0 from 6.1. 

In SOPC Builder, I use New Component editor for external RAM but have problems.   I created Avalon MM tristate slave and signals for custom component: address 18 input data 16 bidir byteenable_n 2 input chipselect_n 1 input read_n 1 input write_n 1 input   This component was instantiated as a verilog file and connected to the tristate bridge. No warning were issued and the system was generated successfully. But only data port appeared in .bdf file.   In another component I created Avalon MM slave and signals: address,writedata and write_n, but there is no port in top level design. How to resolve this problem?   thanks,

[Altera_Forum]

To be seen from outside, a port has to be declared as export in Avalon Conduit interface. (http://www.altera.com/literature/manual/mnl_avalon_spec.pdf) 

 So declare a signal according to its function for the processor side (e.g. address; Avalon MM slave), and declare one as export (Avalon Conduit) for the external side, and make the connection between them inside your component.  Jérôme