Hi, I'm beginner in VHDL, trying to get a true simulation result.
------------THIS'S THE CODE--------- library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; entity ensonled is port ( CLK_50MHz: in std_logic; myLED: out std_logic ); end ensonled; architecture ensonled of ensonled is signal counter:integer range 0 to 24999999; signal CLK_1Hz:std_logic :='0'; begin prescaler: process(CLK_50MHz) begin if rising_edge(CLK_50MHz) then if counter<25000000 then counter<=counter+1; else CLK_1Hz <= not CLK_1Hz; counter <= 0; end if; myLED<=CLK_1Hz; end if; end process prescaler; end ensonled; --------------------- THIS'S THE TEST BENCH CODE------------- LIBRARY ieee; USE ieee.std_logic_1164.all; ENTITY ensonled_vhd_tst IS END ensonled_vhd_tst; ARCHITECTURE ensonled_arch OF ensonled_vhd_tst IS -- constants -- signals SIGNAL CLK_50MHz : STD_LOGIC; SIGNAL myLED : STD_LOGIC; COMPONENT ensonled PORT ( CLK_50MHz : IN STD_LOGIC; myLED : OUT STD_LOGIC ); END COMPONENT; BEGIN i1 : ensonled PORT MAP ( -- list connections between master ports and signals CLK_50MHz => CLK_50MHz, myLED => myLED ); --CLK_50MHz <= not CLK_50MHz after 20 ns/2; clk_gen_proc : process begin if CLK_50MHz /= '1' then CLK_50MHz <= '1'; else CLK_50MHz <= '0'; end if; wait for 20 ns; end process; END ensonled_arch; ----------------------------------- In simulation, I always getting 'myLED' as 0 after first rising edge of Clock. And additionally, for one time, I got a result like I desired, but whenever i tried it out over again, failed. Never changed the code, it was same. But it doesn't give a damn any more. Why? Please help me. https://alteraforum.com/forum/attachment.php?attachmentid=14932&stc=1 https://alteraforum.com/forum/attachment.php?attachmentid=14932&stc=1 https://alteraforum.com/forum/attachment.php?attachmentid=14932&stc=1Link Copied
counter is always going to be less than 25000000 because you set its max range to 24999999.
ahh Thanks, though i've changed it, unfortunately giving same result:( what's wrong?
how long are you running the simulation for?
You need to run it for more than 500 ms for myLED to go high.For more complete information about compiler optimizations, see our Optimization Notice.