PLL Clock Frequency

[Altera_Forum]

I'm creating a block schematic and am using LPM_PLL megafunction. The input frequency is 44MHz, but it won't let me create an output frequency lower than 9.3 MHz. 

 Does anyone know how I can get a 5.5 MHz Clock out?  Thanks.

[Altera_Forum]

What FPGA are you using? Because some FPGA families can't generate clocks lower then 10MHz in the PLL, you can check it in the Handbook of the family. You need to make clock dividers to get lower frequencies.

[Altera_Forum]

--- Quote Start ---  You need to make clock dividers to get lower frequencies.  --- Quote End ---     If you do divide the higher-speed clock with a register, it would be better to create a clock enable with the divided-down signal instead of driving a lower-speed clock directly from the divide-down register. For example, use the PLL to create a clock that is twice as fast as the needed frequency, then use a divide-by-2 signal as a clock enable. You said you are using a schematic. Choose register primitives that show the clock enable port. Some megafunctions also have a clock enable port available; it might be an option you have to select.  If you drive a lower-speed clock directly from the divide-by-2 register instead of using a clock enable, then it would be best not to have any synchronous paths crossing to or from the divided-down clock domain. In other words, set up the design so that the timing on cross-domain paths does not matter, and use cut-path (false-path) settings to tell Quartus to ignore the timing on the cross-domain paths. (There's also a way to do it with clock settings.) That way the clock skew won't matter for paths that cross between clock domains. Also make sure the divided-down clock is on a global line (you can force this in the Assignment Editor if the Fitter doesn't make the clock global automatically) to minimize clock skew between registers within the domain.

[Altera_Forum]

--- Quote Start ---  If you do divide the higher-speed clock with a register, it would be better to create a clock enable with the divided-down signal instead of driving a lower-speed clock directly from the divide-down register. For example, use the PLL to create a clock that is twice as fast as the needed frequency, then use a divide-by-2 signal as a clock enable. You said you are using a schematic. Choose register primitives that show the clock enable port. Some megafunctions also have a clock enable port available; it might be an option you have to select.   --- Quote End ---    The only megafunction that I could find that had a clock enable was LPM_FF. I'm not sure if this is what you were refering to or not?  Also, I'm using the Cyclone II FPGA.  Thanks.

[Altera_Forum]

For register primitives, I meant primitives such as DFFE that have an ENA port. These might be all you need instead of LPM_FF. 

 For megafunctions, "RAM: 2-PORT" is an example of what I meant. For this particular megafunction, the MegaWizard has a checkbox called "Create one clock enable signal for each clock signal" at "Parameter Settings --> Regs/Clkens/Aclrs". Some megafunctions might have optional clock enables buried behind a "More Options" button.

[Altera_Forum]

--- Quote Start ---  If you do divide the higher-speed clock with a register, it would be better to create a clock enable with the divided-down signal instead of driving a lower-speed clock directly from the divide-down register. For example, use the PLL to create a clock that is twice as fast as the needed frequency, then use a divide-by-2 signal as a clock enable.    --- Quote End ---    Could you explain it in detail ? Now I am using a PLL in my project to generate a global clock(clk). The frequency of clk is beyond my need. What should to do ? Divide clk to the new one I need, or change the PLL to a divider to generate my needed clock ?  Thanks. hapyang

[Altera_Forum]

If the frequency you need can be provided by the PLL, then use the PLL to divide the input clock.

[Altera_Forum]

The clock I need is lower than K , so I need a divider to generate the clock, is it ? 

 In my project , I use some timer to control different domains ,the clocks I use are more than three and the frequencies of which are all under K.  Some suggestions please. Thanks very much.

[Altera_Forum]

If you want to create Freqs with less than 10Megs, I assume that one could do this manually in most cases. 

 >44MHz, how can I get a 5.5 MHz Clock out"  A Division of 8 might work.  If you observe stability problems, you'll have the change your design to an "enable based" design, reacting on every second clock (and using 11Megs of course).

[Altera_Forum]

If you drive a clock directly with a register instead of using a clock enable, see http://www.alteraforum.com/forum/showthread.php?t=2388 for things you need to consider.