Problem in generating clock from constrained PLL clock

[Altera_Forum]

Hi all,  

 I am using Time quest for constraining clocks. I was able to constrain PLL clock from "derive_pll_clocks". In my case i have to generate other clocks from this PLL clock, i am trying to constrain those clocks by generating in time quest. But i am not able to do so, please guide me.   FYI:This is the command for generating clock,  # create_generated_clock -name {serialCommRxSynchronizeSignal} -source [get_ports {SYSTEM_CLOCK_MAIN_1}] -divide_by 2 [get_nets {PLL_12|altpll_component|_clk0}]   serialCommRxSynchronizeSignal - Clock to be generated SYSTEM_CLOCK_MAIN_1 - System Clock clk0 - PLL output   Thank you.

[Altera_Forum]

Your command makes no sense: you have three clocks there. 

 By "PLL clock", I assume you mean a PLL output clock.  The syntax for create_generated_clock is create_generated_clock -name <name> -source <sourceClock> -divide_by 2 <targets>  <name> is just that, a pretty name to give to it.  <sourceClock> is the source clock object.. If your clock is being generated from a PLL output clock, then it will be something like  [ get_pins -hierarchical {PLL12|altpll_component|auto_generated|pll1|clk[0]} ]  <target> will be the objects where your generated clock comes from. Typically, it will be a register or so.