A simple answer if there is one (please)

Altera_Forum · ‎04-02-2010

Dear All,

I've read in multiple posts etc that I'm not allowed to use ripple clocks etc but would anyone be so kind as to give me the actual Verliog code (without using a PLL) for how to produce a 1KHz clock from a 50MHz clock. Everything I've read says use "clock enables" but I'm such a newbie that I have no idea what that means and all the references give me lots of pretty diagrams but no code... please put me out of my ignorant misery.

Thanks,

Lomax

Altera_Forum · ‎04-02-2010

Divide 50 MHz by 50000 and get a signal that's '1' for one clock period and '0' for 49999. Use it as clock enable in a synchronous process, that's clocked by the 50 MHz as well.

Clock enable means e.g.

always @(posedge clk50)
begin
  if (cnt_1kHz)
    begin
      cnt_1kHz--;
      ce_1kHz <= 1'b0;
    end
  else
    begin
      cnt_1kHz <= 16'd49999;
      ce_1kHz <= 1'b1;
    end;
  if (ce_1kHz)
    begin
      // This code executes at 1 kHz speed
    end
end

Altera_Forum · ‎04-02-2010

Perfect, no more warnings and I appear to be able to "export" the result for want of a better phrase :

reg [15:0] paddleCount = 16'd0;

reg PADDLE_CLOCK;

always @(posedge CLOCK_50)

begin

if (paddleCount)

begin

paddleCount <= paddleCount - 16'd1;

PADDLE_CLOCK <= 1'b0;

end

else

begin

paddleCount <= 16'd49999;

PADDLE_CLOCK <= 1'b1;

end

always @(posedge PADDLE_CLOCK)

begin

etc

I'm still not sure why the original didn't work - was it the "wire" as opposed to the "reg"?

wire PADDLE_CLOCK;

assign PADDLE_CLOCK = (paddleCount == (16'd50000));

always @(posedge CLOCK_50)

begin

if (PADDLE_CLOCK)

paddleCount <= 16'd0;

else

paddleCount <= paddleCount + 16'd1;

end

Many thanks for your help

Lomax

Altera_Forum · ‎04-02-2010

Your clock divider as such should work as well, although it divides by 50001.

The problem is in using PADDLE_CLOCK in an edge sensitive expression. It's a formed by combinational logic and has glitches. Making PADDLE_CLOCK a register and assigning it inside the posedge block would avoid this problem. But it's still a ripple clock, delayed in relation to CLOCK_50. The problem arises with signals, that are used in both clock domains CLOCK_50 and PADDLE_CLOCK. Using PADDLE_CLOCK as a clock enable instead keeps one clock domain for the design.

Altera_Forum · ‎04-05-2010

Just curious - does it increase the power when using enables this way instead of a 1KHz clock because now we have to route both the enable and the clock through out the device? And if it is a large device then 50MHz is still a lot of unnecessary toggles.

Altera_Forum · ‎04-05-2010

--- Quote Start ---

does it increase the power when using enables this way instead of a 1KHz clock

--- Quote End ---

Basically, yes. With a reasonable system clock (e.g. 50 MHz), it isn't a problem with usual designs. Furthermore, operating consderable parts of a design with 1 kHz clock frequency is rather a lab exercises problem than a typical situation of real world FPGA design.

Generally, you're free to use ripple clocks if they are helpful to save power. But in most designs, these slow clock domain partitions have to cooperate with other design parts. Timing closure of domain crossing signals will become much more difficult with ripple clocks. That's why their usage is discouraged.