Problem with Array Operation

Altera_Forum · ‎06-09-2009

Hi,

I'm having a problem with the following code:

module learning(datain,address,datawrite,dataread,
dataout,dataout_,a1,a2,temp1,temp3,temp2);
parameter length_of_data = 16;
parameter bits_of_address = 4;
input datain;
input address;
input datawrite,dataread;
output dataout,dataout_;
output a1,a2;
output temp1,temp2,temp3;
reg a1,a2;
reg arr ;
reg arr_ ;
reg temp1,temp2,temp3;
assign dataout =dataread? arr  : 0;
assign dataout_=dataread? arr_ : 0;
always@(posedge datawrite)
begin
arr=datain;
a1=datain;
a2=datain;
temp1=arr;
temp2=temp1*a1;
temp3=temp2/a2;
arr_=temp3;
end
endmodule

i cannot understand why 'temp3' is showing unusual values. Please help...

Altera_Forum · ‎06-10-2009

Are you simulating this or actually running it in a part? I'm not sure you are generating the logic you expect. There is a massive amount of combinatorial logic created here.

Here is what things will be every time datawrite goes high:

arr[address] will be datain

a1 will be datain

a2 will be datain

temp1 will be datain (Is this what you wanted?)

temp2 will be datain * datain (Is this what you wanted?)

temp3 will be (datain * datain) / datain (Is this what you wanted? Should be equivalent to datain)

arr_[address] will be (datain*datain) / datain (Is this what you wanted?)

Is it possible that you are abusing the Verilog blocking "=" operator and should instead be using the non-blocking operator "<="?

Jake

Altera_Forum · ‎06-10-2009

thanks for the reply Jake :)

it was just a test file...... and yes, i just wanted that temp3 will show the value of datain and also stor the value to arr_address.......... but i don't know why, it is not happening!!! i am using quartus II 7.2 sp3 and there is no error messege........... what do you think has happened??

Altera_Forum · ‎06-10-2009

1 - What are you getting for temp3?

2 - Are you meeting timing requirements on this?

3 - What device are you using (including speedgrade)?

Jake