Problem with use of real type in VHDL

[Altera_Forum]

Posted: Wed Apr 09, 2008 8:01 pm Post subject: Problem with use of real type in VHDL  

 --------------------------------------------------------------------------------   Hi all  I am using quartusII version4 for compiling and simulating VHDL codes.  I have a problem with use of real type in VHDL, i am using mathpack and write:  (download from http://www.csee.umbc.edu/help/vhdl/stdpkg.html)   library IEEE;  use IEEE.math_real.all;   but i has a lot of error when compiling such as  Error: VHDL package error at mathpack.vhd(45): package math_real already exists  Error: VHDL Use Clause error at mathpack.vhd(1175): design library ieee does not contain primary unit math_real  Error: VHDL error at mathpack.vhd(1187): object real is used but not declared   Kind regards for your help _________________ Vahid

[Altera_Forum]

Hello Vahid, 

 I think I read in the help documents that the real type is not supported by Quartus.  Best regards,  Blacktom

[Altera_Forum]

The software already has a version of the math_real package in the IEEE library. You're getting the "math_real already exists" because you're trying to compile another version into the same library. Most decent synthesis tools will allow you to use real types for generics and constants but not for signals. Quartus II is no exception.