Help！I have completed my FPGA design with dspbuilder. I used the 'Signal Compiler' in it to generate a project for using in quartus. Now I want to analyze the power with the powerplay in quartus. but i found the dynamic power analysis in report is zero. I saw some information that I should use modelsim to generate a '.vcd' file and import it into powerplay to get dynamic power analysis. Unfortunately, I fail again in simulating. My design only have two inputs 'clk' and 'aclr', and an 16 bits output. I wrote the testbench like this: ...... init : PROCESS -- variable declarations BEGIN aclr<='1'; -- code that executes only once WAIT; END PROCESS init; always : PROCESS constant clk_period:time:=20ns; constant DELAY : time := 0 fs; -- optional sensitivity list -- ( ) -- variable declarations BEGIN -- code executes for every event on sensitivity list wait for DELAY; loop Clock<='0'; wait for clk_period/2; Clock<='1'; wait for clk_period/2; end loop; WAIT; END PROCESS always; ...... I can get the expected wave for clk and aclr, but the output is always 'u', the wave is a red line.
now i don't konw how to get correct simulation result or there's any other method to get correct power analysis? Thank you for your read and help in advance.