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Hi,
I am running BER test for 2 FPGAs. I am transmitting from Tx pin of first FPGA and receiving on Rx pin on second FPGA. Using Quartus 23.4 here.
Both are Agilex F-tile F-series FPGAs. There is a total trace length of 13 inches between the FPGAs and the speed is 28Gbps NRZ PRBS31.
I set up a autosweep to sweep through different tap values in order to tune the channel
I notice that the results show negative eye height for many iterations but the corresponding BER is zero (see attached pdf)
How can this be possible?
Negative eye height means that the eye is closed. In this case we should expect maximum BER
Please help me understand what is going on here
Thanks,
Ranjith
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Adding more details:
The insertion loss between the FPGAs is ~15db.
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Hi Ranjith21,
May I know the OPN board number that you use?
Best regards,
zying
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Hi Ranjith21,
Negative eye height value means that the measurement height is calculated by Eye Center-to-top (Middle) minus Eye Center-to-bottom(Middle). For the positive height value, the measurement height is calculated from eye center to the top of the eye.
Best regards,
zying
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Hi Ranjith21,
BER issue always related to channel loss. Please do make sure the RX channel is receiving data before starting eye measurement.
Best regards,
zying
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Hello @ZiYing_Intel
This is the FPGA part number AGFB027R31C2E2V
I have ensured that the RX channel is receiving data before starting eye measurement
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Hi Ranjith,
Could you try to adjust the main tap value?
Best regards,
zying
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Hi Ranjith,
Please do let me know if there is any update on the BER value when you adjust the main tap value.
Best regards,
zying
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I am sweeping different values for main tap as shown in the attached PDF. Still negative eye height with zero BER exists, please refer .pdf attached
Thanks,
Ranjith
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Hi Ranjith,
Could you try to increase the amplitude? Because I assume that the receiver side still have the minimum height limit on there.
From the analog side, the transmitter usually larger a bit than the receiver. The receiver side will have the minimum height limit on there and if the height is smaller than the minimum requirement, the signal might occur a lot error (BER).
Best regards,
zying
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Hi,
Since no hear any feedback from you, I now transition this thread to community support. If you have a new question, feel free to open a new thread to get the support from Intel experts. Otherwise, the community users will continue to help you on this thread.
Best regards,
zying
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Please check my comments. I have updated my responses on 02-20-2024
Please scroll up
Thanks,
Ranjith
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Hi Ranjith,
I now transition this thread to community support. If you have a new question, feel free to open a new thread to get the support from Intel experts. Otherwise, the community users will continue to help you on this thread.
Best regards,
zying

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