Intel® Quartus® Prime Software
Intel® Quartus® Prime Design Software, Design Entry, Synthesis, Simulation, Verification, Timing Analysis, System Design (Platform Designer, formerly Qsys)
16623 Discussions

[Quartus II] How to automate the Compilation?

Altera_Forum
Honored Contributor II
1,990 Views

I want to compile multiple projects at night and check the results (SOF files) at work time. 

 

Is there any script or command line that is equivalent to the 'Play' button (Quartus II menu -> Processing -> Start Compilation) in the Quartus II GUI? I need it very much because I have no time to compile projects at work time. 

 

I am using Quartus II version 8.0 SP1 on Windows XP. The projects make use of Cyclone III device with Nios II processor. 

 

Thank you in advance 

avtx30
0 Kudos
4 Replies
Altera_Forum
Honored Contributor II
572 Views

Yes it can be done. All the individual commands are available from the command line. 

 

Look-up quartus_fit, quartus_map, quartus_asm, quartus_tan. 

 

I actually haven't automated my builds yet, but if you search the Quartus_8.0 help it gives you some very simple examples. (Search "Command-line Script") 

 

(From the help) 

 

Note: The script example below works with a previously existing Verilog HDL file named testproject.v, that contains an entity called testproject. Modify any Verilog HDL file to meet this description and place it in the directory containing the script, or use the following code: 

 

 

 

module testproject(switch[15:0], light[15:0]); 

 

 

 

input [15:0] switch; 

 

output [15:0] light; 

 

 

 

assign light[15:0] = switch[15:0]; 

 

 

 

endmodule 

 

 

 

 

To test this example script: 

 

Create a directory for the project. 

 

Copy the example script and save it in the new directory with the file name shell_example_1.bat. 

 

Copy the Verilog HDL example source code and save it in the new directory as testproject.v. 

 

At the system command prompt, navigate to the new directory. 

 

Type shell_example_1.bat to run the script. 

 

SET PROJECT=testproject 

 

SET TOP_LEVEL_FILE=testproject.v 

 

SET FAMILY=Cyclone 

 

SET PART=EP1C12Q240C6 

 

SET FMAX=80MHz 

 

quartus_map %PROJECT% --family=%FAMILY% --source=%TOP_LEVEL_FILE% 

 

quartus_fit %PROJECT% --part=%PART% --fmax=%FMAX% 

 

quartus_asm %PROJECT% 

 

quartus_tan %PROJECT% 

 

There's also "Generate TCL file, that dumps all the project settings into a TCL script, but doesn't give you the next step. of actually compiling the design. 

 

This is a start anyway. 

 

Pete
0 Kudos
Altera_Forum
Honored Contributor II
572 Views

Once you have created your project in quartus. All you have to do is run quartus_sh --flow <project_name> and your project will compile as if you've pushed the play button. 

 

Jake
0 Kudos
Altera_Forum
Honored Contributor II
572 Views

Hi all, 

 

There is yet another way of night-compilation using DSE(Design Space Explorer).This can be used for finding alternative fittings e.g. scanning a number of seeds ...etc. and usually useful at the end of a project when you get closer to your firing squad and your last days of work. 

 

kaz
0 Kudos
Altera_Forum
Honored Contributor II
572 Views

Thank you all. I will use quartus_sh --flow <flow_name> <project_name> first then explore the DSE. 

 

Bests, 

avtx30
0 Kudos
Reply