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I encountered following internal error.
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Problem Details
Error:
Internal Error: Sub-system: BSYN, File: /quartus/fitter/bsyn/dup/bsyn_qdup.cpp, Line: 1300
parent_candidate.m_rejected_str == nullptr
Stack Trace:
0xaa817: BSYN_QDUP_CANDIDATE_MANAGER::log_duplication + 0x137 (fitter_bsyn)
0xc3106: BSYN_QDUP::run_qdup + 0x4b6 (fitter_bsyn)
0xc06ba: BSYN_QDUP::run_early_qdup + 0x25a (fitter_bsyn)
0x4f2cd: BSYN_QDUP::Run + 0x55d (fitter_bsyn)
0x6561c: BSYN::bsyn + 0x38c (fitter_bsyn)
0x65186: bsyn + 0x666 (fitter_bsyn)
0x65bf2e: `anonymous namespace'::bi_run_bsyn + 0xce (fitter_vpr20kmain)
0x658676: BSYN_CONFIG::run + 0x96 (fitter_vpr20kmain)
0x65c058: bi_bsyn + 0x48 (fitter_vpr20kmain)
0x430ff5: VPR_QI_FACADE::bsyn + 0x85 (fitter_vpr20kmain)
0x430c57: VPR_QI_FACADE::vpr_bsyn_flow + 0x77 (fitter_vpr20kmain)
0x56850: FDRGN_EXPERT::run_vpr + 0x1d0 (fitter_fdrgn)
0x51637: FDRGN_EXPERT::place + 0x177 (fitter_fdrgn)
0x1798f: fit2_fit_place_auto + 0x19f (comp_fit2)
0x16442: TclNRRunCallbacks + 0x62 (tcl86)
0x3c78: fit2_fit_place + 0x368 (comp_fit2)
0x16442: TclNRRunCallbacks + 0x62 (tcl86)
0x17c4d: TclEvalEx + 0x9ed (tcl86)
0xa6a8b: Tcl_FSEvalFileEx + 0x22b (tcl86)
0xa5136: Tcl_EvalFile + 0x36 (tcl86)
0x14ebc: qexe_evaluate_tcl_script + 0x3fc (comp_qexe)
0x13f72: qexe_do_tcl + 0x4b2 (comp_qexe)
0x1a34e: qexe_run_tcl_option + 0x5ee (comp_qexe)
0x18195: QCU::DETAIL::intialise_qhd_and_run_qexe + 0x95 (comp_qcu)
0x290bc: qcu_run_tcl_option + 0x2ec (comp_qcu)
0x19c58: qexe_run + 0x438 (comp_qexe)
0x1ad8a: qexe_standard_main + 0x26a (comp_qexe)
0x2052: qfit2_main + 0x82 (quartus_fit)
0x14a08: msg_main_thread + 0x18 (CCL_MSG)
0x160ae: msg_thread_wrapper + 0x6e (CCL_MSG)
0x20fb0: mem_thread_wrapper + 0x70 (ccl_mem)
0x13f8d: msg_exe_main + 0x20d (CCL_MSG)
0x2918: __scrt_common_main_seh + 0x11c (quartus_fit)
0x17973: BaseThreadInitThunk + 0x13 (KERNEL32)
0x6a270: RtlUserThreadStart + 0x20 (ntdll)
End-trace
Executable: qpro
Comment:
None
System Information
Platform: windows64
OS name: Windows 10
OS version: 10.0
Quartus Prime Information
Address bits: 64
Version: 19.2.0
Build: 57
Edition: Pro Edition
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Sometimes, error can be avoided by lowering clock frequency for FPGA fabric (ex. 100MHz -> 50MHz).
I also encountered same error on 19.1(Windows), 19.1(Linux). 19.2(Linux) not tested yet.
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Hi.
I'm using Stratix10.
Sorry, I can't provide design files.
Following is summary of the design.
Family : Stratix 10
Device : 1SX280LN3F43E2VG
Timing Models : Final
Logic utilization (in ALMs) : 435,765 / 933,120 ( 47 % )
Total dedicated logic registers : 515140
Total pins : 175 / 912 ( 19 % )
Total block memory bits : 9,732,800 / 240,046,080 ( 4 % )
Total RAM Blocks : 1,135 / 11,721 ( 10 % )
Total DSP Blocks : 5,169 / 5,760 ( 90 % )
Total DIB Channels : 0 / 75 ( 0 % )
Total HSSI RX channels : 0 / 48 ( 0 % )
Total HSSI TX channels : 0 / 48 ( 0 % )
Total PLLs : 3 / 88 ( 3 % )
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Can you check your inbox? thanks
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