Recommand approach to do the pin assignments

[Altera_Forum]

If I didn't use pin planner to do pin assignments before hand. After I finish my design, then I need to do pin assignments, what is the recommend approach to do pin assignments in this case? It looks like there should be 3 approaches: 

1. pin planner 2. Assignment editor 3. editing qsf file directly  Pin planner may be not the good choice since it should be used in plan stage. The problem of assignment editor is in each row, I can only edit one property of pins (maybe I use in wrong way?). So it looks like editing the qsf file is the best approach. Anyone has some suggestions ?  Thanks.

[Altera_Forum]

I prefer to edit the .qsf file directly even though that's not the official/approved way to do it. But you have to know what you're doing and what the available settings are to do it that way. I use the pin planner for checking pin assignments but not for entering them. 

 If you like the gui approach you can use the Pin Planner after the design is complete. Just compile the design with no pin assignments, then use the Pin Planner afterward to go in and edit the assignments that Quartus picked. At least I think that should work.

[Altera_Forum]

I've recently started doing it in the VHDL architecture like this: 

 attribute chip_pin : string; attribute chip_pin of KEY1 : signal is "@88"; attribute chip_pin of KEY2 : signal is "@91";  It's described here:  http://quartushelp.altera.com/13.0/mergedprojects/hdl/vhdl/vhdl_file_dir_chip.htm

[Altera_Forum]

--- Quote Start ---   If you like the gui approach you can use the Pin Planner after the design is complete. Just compile the design with no pin assignments, then use the Pin Planner afterward to go in and edit the assignments that Quartus picked. At least I think that should work   --- Quote End ---    Yes, it should work in that way. And personally I prefer this way. Because it provides information about direction of pin, bank and especially voltage level. This helps to ensure we select correct voltage level for pin based on actual pin voltage from schematic. And this also helps to cross verify that PCB designer have routed signal to correct bank ( to be specific, incoming signal's voltage level meets voltage level in which it has been routed and same for outgoing signal).  In past, I was used to use assignment editor. And I was only assigning pin locations. During one project, I got schematic at early stage of board design and I did same thing. But later on we came to know that one 3.3V level incoming signal was routed to bank having lower voltage level(1.8v). So that board needed to be revised. If I would had checked voltage level at earlier stage, its revision could have been avoided. Hope sharing this would help others to avoid similar mistake.   Warm Regards, Bhaumik

[Altera_Forum]

In my opinion, the best way is to create a Tcl script that implements the pin constraints, including any additional constraints like slew rate, output current, I/O voltage, etc. 

 Take a look at any of the example designs I have posted.  DE0-nano: http://www.alteraforum.com/forum/showthread.php?t=45927  BeMicro-CV http://www.alteraforum.com/forum/showthread.php?t=43992  1. Run the synthesis script for these projects.  2. Use "Project->Generate Tcl file for Project" to generate a Tcl file with all the Quartus settings.  3. Open the pin planner, right-click in the pin planner view and add extra columns for the various I/O settings.  Now you can compare the pin planner view and the generated Tcl file to the scripts/constraints.tcl script.  The constraints.tcl file contains a list of Tcl key-value pairs that correspond to the pin planner view, the key-value pairs are then converted to the Tcl constraints seen in the generated Tcl file. The key-value pair format makes it easier to see all the constraints associated with one pin (and is similar to Xilinx's .ucf format file).  Cheers, Dave

[Altera_Forum]

Thanks very much for all these valuable replies!