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SR latch test bench help

Altera_Forum
Honored Contributor I
1,626 Views

Hey im not sure how to make a testbench for an sr latch, the code ive made is shown below for the latch and the testbench. 

 

for the latch  

 

library ieee; 

use ieee.std_logic_1164.all; 

 

 

entity tut6a is  

port (  

end tut6a; 

 

 

architecture struct of tut6a is 

signal r1 , s1, qa , qb : std_logic; 

attribute keep : boolean; 

attribute keep of r1 , s1 , qa , qb : signal is true; 

begin 

 

 

r1 <= r and clk; 

s1 <= s and clk; 

qb <= not (r1 and qa); 

qa <= (s1 and qb); 

q <= qa; 

 

 

end struct; 

 

for the testbench 

 

library ieee; 

use ieee.std_logic_1164.all; 

 

 

entity Testbench6a is  

end Testbench6a; 

 

 

architecture struct of Testbench6a is 

component tut6a 

port ( clk , r , s : in std_logic; 

qa , qb , rl , sl : out std_logic); 

end component; 

signal s , r , q : std_logic := '0'; 

signal rl , sl , qa , qb : std_logic := '0'; 

signal clk : std_logic := '1'; 

begin  

inst1 : tut6a port map( clk ,  

r , 

s , 

qa, 

qb, 

rl, 

sl ); 

process  

begin  

 

 

s <= '1'; 

r <= '0'; 

wait for 10 ns; 

s <= '0'; 

r <= '1'; 

wait for 10 ns; 

s <= '1'; 

r <= '1'; 

 

 

wait for 10 ns; 

end process; 

end architecture;
0 Kudos
3 Replies
Altera_Forum
Honored Contributor I
275 Views

What exactly do you need help with? It looks like you are following a tutorial (given an entity name name tut6a). If so, did you read something in this tutorial, or the ones before, regarding port mapping and such things?

Altera_Forum
Honored Contributor I
275 Views

Im having problems getting an output in the simulator in modelsim for rl sl qa and qb, i changed the code a bit so it shows r s and q on the simulator. 

 

library ieee; 

use ieee.std_logic_1164.all; 

 

entity Testbench6a is  

end Testbench6a; 

 

architecture struct of Testbench6a is 

component tut6a 

port ( clk , r , s : in std_logic; 

q : out std_logic); 

end component; 

signal s , r , q : std_logic := '0'; 

signal rl , sl , qa , qb : std_logic := '0'; 

signal clk : std_logic := '1'; 

begin  

inst1 : tut6a port map( clk ,  

r , 

s , 

q ); 

process  

begin  

 

s <= '0'; 

r <= '0'; 

wait for 10 ns; 

s <= '1'; 

r <= '0'; 

wait for 10 ns; 

s <= '0'; 

r <= '1'; 

wait for 10 ns; 

s <= '1'; 

r <= '1'; 

 

wait; 

end process; 

end architecture;
Altera_Forum
Honored Contributor I
275 Views

 

--- Quote Start ---  

Im having problems getting an output in the simulator in modelsim for rl sl qa and qb, i changed the code a bit so it shows r s and q on the simulator. 

 

--- Quote End ---  

 

Do you see rl sl and both q's in the simulator but do they have the value 'U' or do you not see them at all?
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