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Valued Contributor III
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Size of parameter

I'm building DDR SDRAM controller for DK-START-3C25N board. I have originally set size of FSM register as 6 and specified parameters of FSM states with size 6. But then I reduced size of state machine register to 4 thus parameter's size was reduced either: 

reg[3:0] fsm_state; 

............................... 

parameter [3:0] // FSM states 

IDLE = 4'h0, 

MRS = 4'h1, 

SR = 4'h2, 

AR = 4'h3, 

RA = 4'h4, 

READ = 4'h5, 

BS = 4'h6, 

WRITE = 4'h7, 

READA = 4'h8, 

WRITEA = 4'h9, 

PC = 4'hA; 

 

However during compilation Quartus outputs the following warning messages: 

Warning (10230): Verilog HDL assignment warning at parameters.v(3): truncated value with size 6 to match size of target (4) 

.................................. 

Warning (10230): Verilog HDL assignment warning at parameters.v(13): truncated value with size 6 to match size of target (4) 

 

Looks like it still treats parameter's size as 6 even though I've changed it to 4 and FSM register size is also 4. 

Even though this warning does not cause any harm and final design works I still would like to know the reason for this warning. Any suggestions are very welcome. 

I'm using Quartus II 9.0 Web Edition.
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Valued Contributor III
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Re: Size of parameter

I have found the answer - I did not update symbol in the *.bdf file as parameter values recorded in that file. After symbol is updated the warning is gone.

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