Strange problem in synthesis of counter

[Altera_Forum]

Hello, 

I am currently writing a learning module on creating a mod-counter. When I attempt to demonstrate the concept of a mod-6 counter using the 4count symbol and a NAND2 as feedback to the CLRN port, I can not count beyond binary 3. The configuration is as follows: QB and QC output of 4count connected to inputes of NAND 2. Output of NAND2 tied to CLRN of 4count.   Both vector waveform and programming DE1 has the error. Any ideas?

[Altera_Forum]

The problem is caused the asynchronous character of the 4count clrn input. You can't build a reliable counter this way. Use a synchronous reset from 5 to 0 instead.

[Altera_Forum]

Thank you! It is funny that I have five books that say otherwise so it was quite frustrating trying to demonstrate a mod counter. The solution you provided works great.

[Altera_Forum]

The asynchronous feedback modulo logic only works with an asynchronous ripple carry counter. Here the stages are toggling one after the other. I have build many similar counters with discrete TTL and CMOS logic in the past. 

 4count is a synchronous counter, so all outputs are toggling at the same time. Depending on accidental delays, you can get a reset glitch during the transition 3->4.