Synthesis output for multiple driver within one always

[Altera_Forum]

Hi,  

 I came across a code snippet and has been boggling my mind quite a bit.  The equivalent to the code is below: a is output and x is an internal register always@(posedge clk)  begin  a <= 1'b1;  if (x == 1)  begin  a <= 1'b0;  end end My question is this:  What happens when x is 1?  I know simulation results show 0. It takes the last value, but that's not what I'm looking for.  What happens on the hardware? What signal is prioritized? How does the synthesis tool interpret this?  Technically speaking, isn't this situation (X==1) a multiple driver issue?     Thanks in advance. 

[Altera_Forum]

No, it is not. a will be as simulation - it will be 0 when x = 1 and 1 when x = 0 

 This is just a registered inverter. A single always block can always be condensed into logic (and registers if it is a synchronous process). For any given event, there is a single output. You only get multiple drivers with more than 1 always blocks or assignments as multiple events cause multiple drivers on the same signal.

[Altera_Forum]

I see.  

However, I am not completely clear on this.   My understanding of multiple drivers is this:  You have a flop. Two signals are driving the input of the flop at the same time - Which cannot be possible.   Now, in this code. considering two scenarios by itself.  a<= 1; is an unconditional non-blocking statement. This takes place every clock cycle.  On the hardware I believe this to be a gnded wire connected to the D input of the flop.   if(x==1) a<=0; This would be a mux whose output is driving the input of the D flip flop.   Looking at the above two conditions, when x equals one. We have two wires with different values driving the input of the flop. Could you please tell me how different this is from a multiple driver?   Although this would make sense if  always@(posedge clk)  begin  a<= 1;  if(x==1)  a <= 0;  end   is same as   always@(posedge clk)  begin  if(x==1)  a<=0;  else  a<= 1;  end   Your help is appreciated. Thanks

[Altera_Forum]

Re-writing the code with comments might help you understand this .. 

  always @(posedge clk or posedge rst) begin if (rst) begin // Reset values a <= 1'b0; b <= 1'b1; end else if (x == 1) begin // Defaults a <= 1'b0; b <= 1'b1; // Over-rides if (x) begin a <= ~a; end if (~y) begin b <= 1; end end end   This style of code can is useful in the combinatorial process of an FSM, as you can ensure that all outputs have assignments.  The synthesis tool infers that the "last assignment" to the output is the winner and generates the combinatorial logic feeding the register accordingly.  Cheers, Dave

[Altera_Forum]

--- Quote Start ---  I see.  However, I am not completely clear on this.   My understanding of multiple drivers is this:  You have a flop. Two signals are driving the input of the flop at the same time - Which cannot be possible.   Now, in this code. considering two scenarios by itself.  a<= 1; is an unconditional non-blocking statement. This takes place every clock cycle.  On the hardware I believe this to be a gnded wire connected to the D input of the flop.   if(x==1) a<=0; This would be a mux whose output is driving the input of the D flip flop.   Looking at the above two conditions, when x equals one. We have two wires with different values driving the input of the flop. Could you please tell me how different this is from a multiple driver?   Although this would make sense if  always@(posedge clk)  begin  a<= 1;  if(x==1)  a <= 0;  end   is same as   always@(posedge clk)  begin  if(x==1)  a<=0;  else  a<= 1;  end   Your help is appreciated. Thanks  --- Quote End ---    It is two inputs to the flop - but the if statement builds you a mux - one input is 1, the other is 0. Select is connected to x.