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Hi,
TQ is giving me this message when I run the rskm_report. Info: No dedicated SERDES Receiver circuitry present in device or used in design I do have an LVDS receiver instantiated on my design so I'm not sure what I'm missing. Regards, RobLink Copied
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I should have mentioned I will be using either a Cyclone 3 or 4 device.
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I believe we need to separate between the concept of lvds and serdes.
lvds is about the io voltage aspect (Rx or Tx) serdes : serialser/deserialiser with associated pll etc.- Mark as New
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Right, I have a SERDES receiver implemented using a PLL. Actually I use the ALTLVDS_RX MF
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In that case, well you know you are using it so either the tool is lieing or that the serdes is implemented in another way ! I actually have the same warnings in my system with 32 serdes instantiated (serialisation factor 2:1) but Timequest says no serdes used. I just ignore it.
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I'm trying to figure out my RSKM by using TQ and the rskm_report command. So I suppose that if TQ won't report it, then I have use the Tsu and Thld times reported by TQ to calculate the RSKM.
RSKM = (TUI - SW - TCCS)/2 TUI : Time Unit Interval SW : Sampling Window TCCS: Transmitter channel to channel skew Tsw = Tsu + Thd + PLL jitter- Mark as New
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I just checked the resource section and realised that in my case the serdes were implemented as ddio.
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--- Quote Start --- I'm trying to figure out my RSKM by using TQ and the rskm_report command. So I suppose that if TQ won't report it, then I have use the Tsu and Thld times reported by TQ to calculate the RSKM. RSKM = (TUI - SW - TCCS)/2 TUI : Time Unit Interval SW : Sampling Window TCCS: Transmitter channel to channel skew Tsw = Tsu + Thd + PLL jitter --- Quote End --- Well, if that is the relevant equation then it should work out correctly if you have correct tSU/tH at the input pins. The tSU/tH will be correct if you have entered tCO of external device for set_input_delay's (+effect of board delays).
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Rob, The report_rskm and report_tccs TimeQuest reports are only valid for devices that have the SERDES implemented in hard silicon (e.g. Stratix families). The Cyclone families use DDIO and logic to implement the SERDES, and therefore cannot use these commands. In the Cyclone families, these interfaces are times using the standard micro-model timing just like any other standard I/O interface.
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