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Altera_Forum
Honored Contributor I
888 Views

Timing Analysis: express frequency uncertainty of external oscillator

An external oscillator is connected to my FPGA. Its signal is used as a clock. There is an uncertainty of the oscillator frequency. The minimum frequency is 20 MHz and the maximum frequency is 25 MHz. How can I respect this uncertainty in my *.sdc file for time analysis? 

 

Is the following correct and reasonable? 

# maximum frequency 25 MHz -> period duration = 40 ns# minimum frequency 20 MHz -> period duration = 50 ns# ==> period duration = 45 ns +/- 5 ns 

create_clock -name {osc} -period 45 [get_ports {osc}] 

set_clock_uncertainty -from osc -to osc 5 

 

 

Are the results the same, if the *.sdc file contains the following? 

 

create_clock -name {osc} -period 40 [get_ports {osc}] 

create_clock -name {osc} -period 50 [get_ports {osc}] -add 

 

 

Is there a better or simpler way to respect this uncertainty?
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3 Replies
Altera_Forum
Honored Contributor I
46 Views

That's not what the set_clock_uncertainty is for. 

 

Refer to the 'timing analyzer set_clock_uncertainty command' (https://www.altera.com/support/support-resources/design-examples/design-software/timinganalyzer/cloc...) for details. 

 

For your design - assuming a traditional static design consisting of registers and logic - you 'simply' need to constrain it for your faster clock. Providing it runs at 25MHz it'll run quite happily at 20MHz. 

 

You may need to be careful if you use PLLs or other timing related IP. 

 

Cheers, 

Alex
Altera_Forum
Honored Contributor I
46 Views

 

--- Quote Start ---  

That's not what the set_clock_uncertainty is for. 

--- Quote End ---  

 

I already suspected it. 

 

 

--- Quote Start ---  

Providing it runs at 25MHz it'll run quite happily at 20MHz. 

 

You may need to be careful if you use PLLs or other timing related IP. 

--- Quote End ---  

 

Thanks a lot!
Altera_Forum
Honored Contributor I
46 Views

 

--- Quote Start ---  

For your design - assuming a traditional static design consisting of registers and logic - you 'simply' need to constrain it for your faster clock. 

--- Quote End ---  

 

Which design would not work with this simple solution, for example? And what could I do then? Is this beyond the scope of the timing analyzer?
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