Timing Simulation Quartus9.1sp1

[Altera_Forum]

Hallo all there, 

 i have a question concerning the Timing Simulation in Quartus.  In Quartus, via Assignements > settings > EDA Tool Settings > simulation  i chose ModelSim as the tool, output format vhdl and an output folder.  our project is normally not started directly in the GUI, but in a shell (we use linux) with a ruby script. I want to ask if anybody know where do i have to put this setting (is it already in the .qsf of the Quartus project or do i have to set up a command in the ruby file?) and how does this command look like?  if my question is not clear enough, please say then i try to explain it in a better way  thanks

[Altera_Forum]

everything in Assignments > Settings should be the qsf. the simulation stuff is there, open it up and look for assignments that start with EDA. for example: 

 set_global_assignment -name EDA_SIMULATION_TOOL "ModelSim (VHDL)"

[Altera_Forum]

thanks, 

i will try :-)

[Altera_Forum]

it works, thanks 

 do you have experience with the simulation settings in quartus? is it possible that there is a tb generated? with the stimi which are needed?  regards

[Altera_Forum]

Altera IP including SOPC Builder auto-generates a test bench, otherwise you'll have to write it yourself.

[Altera_Forum]

ok, 

so for a big project (including a NIOS Processor, and many IP Cores) it is not possible, i can only let create a TB-File for my Top Level File which instantiates the Top as a Device Under Test, the rest should be written by myself.  thanks a lot for your help