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I need to program an 8 bit shift register, which will be used in a 4-bit multiplier.
Basically, this is what it should do: 1.- Receive inputs x (multiplier), sum (this comes from the adder segment of the multiplier), done, ad, sh, load 2.- WHen it receives the load signal, it must take the input values x 3.- when it gets the done signal, it must stop working 4.- when it gets the ad signal, it must replace the last 4 bits with the sum, also, when it gets sh it must shift However, I don't seem to get the expected results. This is the code:LIBRARY IEEE;USE ieee.std_logic_1164.all;
Entity registro8 IS
PORT (load, sh, ad, Clock, done, z : IN STD_logic;
x,sum : IN STD_logic_vector (3 downto 0);
m : OUT STD_logic;
w : OUT STD_logic_vector(7 downto 0));
END registro8;
architecture reg of registro8 IS
signal s : std_logic_vector (7 downto 0);
begin
process (load, x, sum, clock, sh, done, ad)
begin
if(done = '0') THEN
if (load = '1') THEN
for i in 4 to 7 loop
s(i) <= x(i-4);
end loop;
for i in 0 to 3 loop
s(i) <= '0';
end loop;
elsif (clock'event and clock = '1') THEN
if (ad = '1') THEN
for i in 0 to 3 loop
s(i) <= sum(3-i);
end loop;
elsif (sh = '1') THEN
s <= s(6 downto 0) & z;
END IF;
end if;
m <= s(7);
w <= s;
end if;
end process;
end reg;
The main problem is that, after loading, the register seems to be deleted. Also, it continues to work, even if the done signal is 1. Thanks for the help
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Read a good book about VHDL, it isn't generic programming language like you are trying to use it.
Your code of the process should look like this: process (clock, reset) begin if(reset = '1') THEN -- here are the initial conditions elsif (clock'event and clock = '1') THEN -- here you write what your shift register does -- if(done = '0') THEN -- if (load = '1') THEN -- if (ad = '1') THEN -- else etc bla bla bla end if; end process;
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