Xilinx 8.1 & Xilinx 14.7 Version will not compile my design

[Altera_Forum]

Hi. 

 I designed the processor DorQ which is attached. It compiles fine in Quartus 2 but my business partners use Xilinx 8.1 & Xilinx 14.7 Version and on these software, it shows errors which are also attached to this thread. Could someone please provide a solution to this problem. Is there a setting we can change on Xilinx 8.1 & Xilinx 14.7 Version that will do away with the error messages. Thanks for your reply. 

[Altera_Forum]

You need the Xilinx forum.

[Altera_Forum]

First off: This is an altera forum. ISE is the Xilinx equivolent of Quartus. Also, 8.1 is 6 years old. Why such an old version? 

 Secondly - wow - what terrible code. I have no idea whats going on , but the use of internal tri-states is not allowed, they will get converted to muxes. Lets have a look at the components:  acff: wire2 and 3 connect to nothing. Hence the buss relay outputs are always connected to 'Z' bcff: see acff (output always 'Z') bus_relay: what is this supposed to do? diode: this isnt a diode, its a wire. DorQ: Wow.   What do you expect to acheive with this code. The Xilinx error indicates that two busses are trying to drive the same signal. This is illegal inside an FPGA.  And your ambition of some massively complex calculation in nanoseconds is a little deluded I think..  -- This model can generate and manipulate a 4464 bit binary digit in nanoseconds.  I'd put a lot of money on this not being the case... Good luck.