Community
cancel
Showing results for 
Search instead for 
Did you mean: 
Altera_Forum
Honored Contributor I
883 Views

Variable declaration place question

the FPGA resource allocation will be different if the variable declaration in different place? 

 

 

//declare the variable i, j, k not in the loop 

int i; 

int j; 

int k; 

 

 

for (...) 

for (...) 

//declare the variable i, j, k in loop 

int i; 

int j; 

int k; 

 

 

 

 

Thanks
0 Kudos
2 Replies
Altera_Forum
Honored Contributor I
20 Views

It certainly does, please read "Intel FPGA SDK for OpenCL Best Practices Guide, Section 1.6.3, Declare Variables in the Deepest Scope Possible".

Altera_Forum
Honored Contributor I
20 Views

Variables declared outside the loops become Global and are visible to the entire code/project. This will mean the memory allocated for the variable will not be released once it is not used. Global variables will tend to keep their memory allocations as long as the project / program is active in memory this taking up a lot of memory space. This is bad design for Embedded designs as Embedded systems have limited RAM.  

 

Its always best to declare variables locally where they tend to be used and then free them once they are out of scope. Only use global variables if needed. This way your code will take up the least memory footprint and can fit into the program memory or the on-chip ROM/flash.
Reply