Walkthrough Jam STAPL Player / JTAG / GPIO / ARM

Altera_Forum · ‎02-09-2013

My problem is that the verify option with the jamplayer fails (Exit code = 11... Device verify failure), see at the end the output...

But to add more context and extra details here my walkthrough:

Let's start by stating my goal: Program an Cyclone 3 or 4 / flash (EP3C16 or EP4CE115 / EPCS16 or EPCS64) from a ARM embedded device by using GPIOs.

From internet search and reading the JAM player was our stating point:

http://www.altera.com/support/devices/tools/jam/tls-jam.html

More precisely I started with this version of the source code:

https://www.altera.com/download/legacy/jam/dnl-player.jsp

I had to fix some problem to compile on Linux:

Build instructions:

- unzip jp_25.exe

- cd jp_25/source

- Rename all files with lowercases:

- for f in `find`; do mv -v $f `echo $f | tr '[A-Z]' '[a-z]'`; done

- chmod 664 *

- vim jamport.h

- Change "#define PORT WINDOWS" TO "#define PORT EMBEDDED"

- Remove the io.h, conio.h, process.h to move them inside the "PORT == WINDOWS" like:

if PORT == WINDOWS# include <windows.h># include <io.h># include <conio.h> # include <process.h>

- To remove the warning :vim jamstub.c +1328 and replace the %ld to %d

- run direct on ARM otherwise use a cross compiler:

gcc -o jamplayer *.c

./jamplayer --help

Here JTAG tutorial that help nicely to start with JTAG:

http://www.fpga4fun.com/jtag.html

# ### Adding my own implementation to communicate to the JTAG from jamstub.c

void initialize_jtag_hardware()

{

// Init the GPIO file descriptor and the rest.

// Add super test that help a lot for debugging the HW the "checkboard pattern" (1010101010) see cyclone handbook for the description.

// Here the short version:

// 1- Do a JTAG reset (tms=1 for 5 clock of the TCK)

// 2- Move to SHIF_IR state

// 3- Set 10 1 in TDI

// 4- Each time a 1 is written on TDI it possible to read something on the TDO and the pattern will be (1010101010)

}

void close_jtag_hardware()

{

// Close all the FD and the rest for GPIO.

}

int jam_jtag_io(int tms, int tdi, int read_tdo)

{

int tdo = 0;

if (!jtag_hardware_initialized)

{

initialize_jtag_hardware();

jtag_hardware_initialized = TRUE;

}

if (specified_com_port)

{

printf("NOT SUPPORTED\n");

}

else

{

// JTAG One tick of the jtag clock.

// Create my own GPIO interface to interact with the JTAG pins: TCK, TMS, TDI and TDO.

// ex: set TCK = 0 set TMS & TDI sleep for half period read TDO. set TCK to 1 sleep half period set TCK = 0 (Just to start and end to zero, looked cleaner on the oscilloscope)

}

if (tck_delay != 0) delay_loop(tck_delay);

return (tdo);

}

# #### Create a JAM file

1- Compile your quartus project it result in sof file

2- Convert the sof file to jic Menu File / Convert Programming Files set:

3- Programming file type: jic

4- Configure device: EPCS64

5- Add Device for the Flash loader: Cyclone IV E -> EP4CE115

6- Add File to the SOF data

7- Click Generate to have your JIC file

8- Open the programmer

9- add jic file

10- check program/configure + verify + blanck check

11- Go Menu File / Create JAM, etc

12- click OK

# ### Program your FPGA with your JAM file

The first thing to understand with the JAM player is that you need to program SFL (Serial Flash Loader) to by able to program the FPGA.

1- jamplayer -aconfigure file.jam

If you add the verbose in the source code, search for verbose and define to one could be easy way:

Here the output of the jamplayer:

./jamplayer -aconfigure BS_C4_SOME.jam

Jam STAPL Player Version 2.5 (20040526)

CRC matched: CRC value = B874

Export: key = "JAM_STATEMENT_BUFFER_SIZE", value = 3547

NOTE "CREATOR" = "QUARTUS II JAM COMPOSER 12.1"

NOTE "DATE" = "2013/02/07"

NOTE "DEVICE" = "EP4CE115"

NOTE "FILE" = "BS_C4_SOME.jic"

NOTE "TARGET" = "1"

NOTE "IDCODE" = "020F70DD"

NOTE "USERCODE" = "FFFFFFFF"

NOTE "CHECKSUM" = "4B533CE2"

NOTE "SAVE_DATA" = "DEVICE_DATA"

NOTE "SAVE_DATA_VARIABLES" = "V0, A12, A13, A25, A42, A93, A43, A92, A94, A95, A103, A104, A105, A109, A111"

NOTE "STAPL_VERSION" = "JESD71"

NOTE "JAM_VERSION" = "2.0"

NOTE "ALG_VERSION" = "63"

root@BrainsightNIRS:~/JAM#

root@BrainsightNIRS:~/JAM# ./jamplayer -aconfigure BS_C4_SOME.jam

Jam STAPL Player Version 2.5 (20040526)

CRC matched: CRC value = B874

Export: key = "JAM_STATEMENT_BUFFER_SIZE", value = 3547

NOTE "CREATOR" = "QUARTUS II JAM COMPOSER 12.1"

NOTE "DATE" = "2013/02/07"

NOTE "DEVICE" = "EP4CE115"

NOTE "FILE" = "BS_C4_SOME.jic"

NOTE "TARGET" = "1"

NOTE "IDCODE" = "020F70DD"

NOTE "USERCODE" = "FFFFFFFF"

NOTE "CHECKSUM" = "4B533CE2"

NOTE "SAVE_DATA" = "DEVICE_DATA"

NOTE "SAVE_DATA_VARIABLES" = "V0, A12, A13, A25, A42, A93, A43, A92, A94, A95, A103, A104, A105, A109, A111"

NOTE "STAPL_VERSION" = "JESD71"

NOTE "JAM_VERSION" = "2.0"

NOTE "ALG_VERSION" = "63"

Device# 1 IDCODE is 020F70DD

configuring SRAM device(s)...

DONE

Exit code = 0... Success

Elapsed time = 00:22:47

The second step is to program the FPGA that will perform an erase, program and verify and this last step is my problem it fail the verify??

Resetting the FPGA reset it properly with the correct code but fail the verify?

Here the output:

./jamplayer -aprogram BS_C4_SOME.jam

Jam STAPL Player Version 2.5 (20040526)

CRC matched: CRC value = B874

Export: key = "JAM_STATEMENT_BUFFER_SIZE", value = 3547

NOTE "CREATOR" = "QUARTUS II JAM COMPOSER 12.1"

NOTE "DATE" = "2013/02/07"

NOTE "DEVICE" = "EP4CE115"

NOTE "FILE" = "BS_C4_SOME.jic"

NOTE "TARGET" = "1"

NOTE "IDCODE" = "020F70DD"

NOTE "USERCODE" = "FFFFFFFF"

NOTE "CHECKSUM" = "4B533CE2"

NOTE "SAVE_DATA" = "DEVICE_DATA"

NOTE "SAVE_DATA_VARIABLES" = "V0, A12, A13, A25, A42, A93, A43, A92, A94, A95, A103, A104, A105, A109, A111"

NOTE "STAPL_VERSION" = "JESD71"

NOTE "JAM_VERSION" = "2.0"

NOTE "ALG_VERSION" = "63"

Device# 1 is EPCS64

erasing ASC device(s) in sector mode...

programming ASC device(s) in sector mode...

CRC verify ASC device(s) in sector mode...

Device verify failure

Exit code = 11... Device verify failure

Elapsed time = 00:27:13

Any ideas about that: Exit code = 11... Device verify failure???

Cheers,

-KA