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Port Connection Error: Output must be connected to a structural net expression...?

Altera_Forum
Honored Contributor II
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Hi All, 

 

I'm getting a frustrating error that appears to be a incorrect syntax involving wires vs reg but i've tried all combinations and can't solve it. So i'm after any help you can please provide. I'll try keep this concise. 

 

what i'm doing 

  1. A module that i'm adapting VGA_Control; i'm trying to connect it to my top model. No need for you to worry about specifics i think atm. 

  2. When i try instantiate the module, i get the error for each output of the module. 

  3. I've ensured that all the module outputs are connected to wires, and this is what my understanding of the IEEE section 12.3.9 is. 

 

 

the error 

 

--- Quote Start ---  

Error (10663): Verilog HDL Port Connection error at TPAD_Basics.v(365): output or inout port "vga_clk" must be connected to a structural net expression 

 

--- Quote End ---  

 

I get this error for all the output signals of that module. 

 

the instantiation - cause of errors 

wire wVGA_Clk; wire oVGA_R; // VGA Red wire oVGA_G; // VGA Green wire oVGA_B; // VGA Blue wire wLCD_DEN; wire wLCD_NCLK; wire wVGA_HS; wire wVGA_VS; VGA_Control VGA2 ( clk(wVGA_Clk), reset_n(KEY), // VGA export interface data_in({wRed, wGreen, wBlue}), iDataValid(1'b1), // vga_clk(LCD_NCLK), vga_hs(), vga_vs(), vga_de(LCD_DEN), vga_r(oVGA_R), vga_g(oVGA_G), vga_b(oVGA_B) ); assign LCD_DEN = wLCD_DEN; //assign LCD_NCLK = wLCD_NCLK; assign VGA_HS = wVGA_HS; assign VGA_VS = wVGA_VS; assign LCD_DIM = 1'b1; assign LCD_R = oVGA_R; assign LCD_G = oVGA_G; assign LCD_B = oVGA_B;  

 

 

port declarations in the module (vga_control) 

// global signal input clk; input reset_n; input data_in; input iDataValid; // VGA export interface output vga_clk; output reg vga_hs; output reg vga_vs; output reg vga_de; output reg vga_r; output reg vga_g; output reg vga_b;
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Altera_Forum
Honored Contributor II
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Did you forget periods when you instantiated the module? 

 

VGA_Control VGA2 

.clk(wVGA_Clk), //<------- like this
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Altera_Forum
Honored Contributor II
3,794 Views

Thank you so much, i am such an idiot.... Absolutely one of those times for me. 

 

I really appreciate you taking the time to look at this for me and slap me back to reality.
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