Warning (14320): Synthesized away node - FFT IP core

[mitsvoid]

Dear All,

I hope you are doing well.

I am currently working on creating a custom IP core to integrate with NIOSII.

The custom IP encompasses configurations for both the wm8731 and FFT. I am now in the process of adding a register map for the FFT signals to the audio wrapper.

The project is structured as follows:

• Custom Verilog audio modules (i2c controller, codec wm controller, fifo buffers) for handling audio.
• A top module to interconnect all these modules.
• A wrapper to facilitate the creation of the register map.
• Programming in C.

I have tested the current setup, and it is functional.

Now, I am attempting to incorporate the FFT IP into my project. For the FFT IP, I have developed:

• Verilog modules for memory and FFT.
• A memory controller that receives data from the audio and with control signals, passes the ADC data to the FFT module.
• Dual-port RAM in both the memory and FFT modules.
• Initialization in the top module alongside other audio modules with no warnings.

However, when attempting to add as wire the fft signals to the wrapper module in order to create the register map, I encounter 1300 warnings, specifically

Warning (14320): Synthesized away node "top:codec_unit|MemoryModule:MemoryModule_inst|ramaudio:audiosamples|altsyncram:altsyncram_component|altsyncram_8ij1:auto_generated|q_b[21]".

I would appreciate your insights on this warnings and how I can resolve them.

Also whether my approach is considered good practice and if it is possible to create a custom IP core with nested IP cores, such as the FFT IP ?

Please note that I don't have a license for the FFT IP, but I have read that it can be used in evaluation mode for 1 hour.

As a postgraduate student working on my thesis, I hope I have clearly articulated my question. Your advice would be highly valuable.

DE2-115 board.

Quartus prime lite 20.1.

Thank you.

[FvM]

Logic is synthesized away if no design output depends on it. Is only shown memory bit qb[21] removed or all memory? In former case, the memory bit is probably unused or driven by constant input data.

This be may either expectable behaviour or happen due to a design flaw. Check operation in simulation.

[mitsvoid]

I have attached a photo hopefully it helps on the design.

The Memory_Module ram stores the audio adc data and the FFT_module ram stores the output from the FFT.

 Is only shown memory bit qb[21] removed or all memory?

 For the entire memory. Please find the attached .txt file with specific warnings.

I tried to check the operation in simulation. However, when I enable the EDA simulation tools, I receive an error 204012. Please check the attached file (Error204012sim.txt) for details.

Could you let me know if this error is due to the license?

Can I simulate the FFT IP core without a license?

Thank you for your prompt reply.

[FvM]

The error message indicates that you are trying to simulate encrypted synthesis files which is isn't possible whether you have a license or not.

You need to generate simulation files during HDL generation and simulate these, it's also possible with free Quartus lite.

[Kshitij_Intel]

Hi Nikolaos,

For this warning, please check below article, that refers to the LVDS IP, but it might be same workaround for your issue as well.

Warning (14320): Synthesized away node "<node... (intel.com)

Please go through it and try it at your end if you are still not able to resolve the issue, please share the simple design to replicate the same warning at my end will try to resolve.

Thank you,

Kshitij Goel

[mitsvoid]

Hi Goel,

I have made some modifications to my design, but the issue still remains.

Please find the attached files containing the top-level entity, memory, and FFT module that I am trying to instantiate in the top module.

The issue has been resolved.

Please can you let me know only if I can simulate the FFT IP core without a license?

Thank you.

[mitsvoid]

Please can you let me know if  I can simulate the FFT IP core without a license?

Thank you.

[Kshitij_Intel · Accepted solution]

Hi,

You can simulate the FFT IP without a license. Follow the steps mentioned 2.5. Simulating Intel® FPGA IP Cores

Thank you,

Kshitij Goel

[Kshitij_Intel]

Hi,

I’m glad that your issue has been resolved, I now transition this thread to community support. If you have a new question. Please login to ‘https://supporttickets.intel.com’, view details of the desire request, and post a feed/response within the next 15 days to allow me to continue to support you. After 15 days, this thread will be transitioned to community support. The community users will be able to help you on your follow-up questions.

Thank you,

Kshitij Goel