The PCIe SOFT IP compiler is mentioned here:
Table 1–2. IP Compiler for PCI Express Features (Part 1 of 2) [page 4 of 372]
We need more PCIe ports and the two built-in HIPs are not enough.
Thank you for the quick reply.
I was not referring to the soft DFE implementation.
What I mean in the PCIe soft IP itself (as opposed to the HIP variant).
It is documented here:
You can select it from IP parameter setting tab under Mega-Wizard .
Shown in image below
I have used Quartus 17.0 std & from IP catalog search PCI and click on IP.
Mega-Wizard window will open up, under IP parameter setting select ether of hard or soft IP option.
Could not find the image mentioned in the last reply.
I am also using Quartus 17. I tried to go to the IP Catalog window and here is what is shown:
Only PCIe HIP is present, no soft IP option. Is there a need to install an optional library?
"Please do follow the steps mentioned"
Click on the IP which will open a Mega-Wizard window and go to parameter setting select ether of hard or soft IP option.
Also please check device family supported from table 1-4 of below link
Thank you for the image. It is very helpful. From you screenshot I see the device selected is Arria II GX. Quartus SW showed the IP compiler for PCI Express after the Arria II device family was installed.
From the document link you provided, looks like support is only for Arria II, Cyclone IV, and Stratix IV. Will there be a version that will support Arria 10 device?
Your recent reply (2018.12.31) maybe for another ticket?
Since I did not ask about testbench generation.
Going back to my original question. From the document link you provided:
Looks like support is only for Arria II, Cyclone IV, and Stratix IV. Will there be a version that will support Arria 10 device?