Why I can't use GENERIC in SOPC Builder 7.2

Altera_Forum · ‎12-06-2007

I used SOPC Builder 7.2 to create custom component.

when my component entity including GENERIC parameters(see below), after adding the component in NiosII system, SOPC Builder will report the following error:

Error: FREQMeasure_WholeSystem_inst: Error (10670): Verilog HDL or VHDL error: cannot create XML design interface for design file FREQMeasure_WholeSystem.vhd. File: E:/Altera_Project/My_IP/FreqMeasure/FREQMeasure_WholeSystem.vhd Line: 1

Error: FREQMeasure_WholeSystem_inst: Quartus II Analysis & Synthesis was unsuccessful. 1 error, 0 warnings

Error: FREQMeasure_WholeSystem_inst: Processing ended: Thu Dec 06 15:24:04 2007

Error: FREQMeasure_WholeSystem_inst: Elapsed time: 00:00:01

Error: FREQMeasure_WholeSystem_inst: Failed to analyze port width.

LIBRARY IEEE;

USE IEEE.std_logic_1164.ALL;

USE IEEE.std_logic_unsigned.ALL;

USE IEEE.std_logic_arith.ALL;

ENTITY FREQMeasure_WholeSystem IS

generic

(

GEN_TOTAL_CHANNEL : integer := 360;

GEN_BENCHMARK_FREQUENCE : integer := 5000;--KHz

GEN_MAX_TARGET_FREQUENCE : integer := 100;--KHz

GEN_T_STROBE_PERIOD : integer := 8; --MicroSecond

GEN_T_STROBE_WIDTH : integer := 4 --MicroSecond

);

port

(

--avalon slave interface

csi_freqmeasure_clock_clk : in std_logic;

csi_freqmeasure_clock_reset_n : in std_logic;

cos_freqmeasure_channel_in_export : in std_logic_vector(GEN_TOTAL_CHANNEL to 0);

avs_freqmeasure_slave_chipselect_n : in std_logic;

avs_freqmeasure_slave_read : in std_logic;

avs_freqmeasure_slave_address : in std_logic_vector(9 downto 0);

avs_freqmeasure_slave_readdata : out std_logic_vector(31 downto 0)

);

END FREQMeasure_WholeSystem;

But if my component entity doesn't including GENERIC parameters(see below), everything go well and I can create NiosII system symbol successfully.

LIBRARY IEEE;

USE IEEE.std_logic_1164.ALL;

USE IEEE.std_logic_unsigned.ALL;

USE IEEE.std_logic_arith.ALL;

ENTITY FREQMeasure_WholeSystem IS

port

(

--avalon slave interface

csi_freqmeasure_clock_clk : in std_logic;

csi_freqmeasure_clock_reset_n : in std_logic;

cos_freqmeasure_channel_in_export : in std_logic_vector(10 to 0);

avs_freqmeasure_slave_chipselect_n : in std_logic;

avs_freqmeasure_slave_read : in std_logic;

avs_freqmeasure_slave_address : in std_logic_vector(9 downto 0);

avs_freqmeasure_slave_readdata : out std_logic_vector(31 downto 0)

);

END FREQMeasure_WholeSystem;

Altera_Forum · ‎12-07-2007

You mean "GEN_TOTAL_CHANNEL downto 0". Otherwise, your range contains 0 elements. The "to" syntax only works for ascending ranges! Try correcting your range. If you still have a problem, file a bug report!

Josh

Altera_Forum · ‎12-27-2007

If you're still having trouble, use all lower-case for your entity name, e.g. freqmeasure_wholesystem rather than FREQMeasure_WholeSystem, then try re-creating your custom component.

Altera_Forum · ‎12-27-2007

Wow...It works now!

Thanks~~~~

It should be a bug of SOPC Builder!