Why am I getting a syntax error in my case structure?

[Altera_Forum]

I am building an ALU control unit in VHDL and I have been getting these errors when compiling. 

 Error (10500): VHDL syntax error at alu_control.vhd(43) near text "when"; expecting "end", or "(", or an identifier ("when" is a reserved keyword), or a sequential statement Error (10500): VHDL syntax error at alu_control.vhd(45) near text "case"; expecting "if"  I have used a very similar case structure when building the actual ALU unit with no erros so I cant seem to find what exactly is wrong.  library ieee ; use ieee.std_logic_1164.all; use ieee.std_logic_unsigned.all;  ---------------------------------------------------  entity alu_control is  port( ALUOp: in std_logic_vector(1 downto 0);   Funct: in std_logic_vector(5 downto 0);  ALUCtrl: out std_logic_vector(3 downto 0));  end entity alu_control;  ----------------------------------------------------  architecture alu_control_arch of alu_control is begin    process (ALUOp, Funct, ALUCtrl)  begin  case ALUOp is  when "00" =>  if Funct = "xxxxxx" then  ALUCtrl <= "0010";  end if;  when "01" =>  if Funct = "xxxxxx" then  ALUCtrl <= "0110";  end if;   when "10" =>  if Funct = "100000" then  ALUCtrl <= "0010";  else if Funct = "100010" then  ALUCtrl <= "0110";  else if Funct = "100100" then  ALUCtrl <= "0000";  else if Funct = "100101" then  ALUCtrl <= "0001";  else if Funct = "101010" then  ALUCtrl <= "0111";  else   ALUCtr <= "xxxx";  end if;  when others =>   ALUCtrl <= "xxxx";  end case;  end process;   end architecture alu_control_arch;

[Altera_Forum]

I think you mean elsif instead of else if. 

elsif continues from last statement, else if starts new if statement.

[Altera_Forum]

That is how I have it written in my code for the ALU unit and it worked. THe simulation for it was correct as well. 

So not sure why it doesnt work here, but changing it to elseif gives this  Error (10500): VHDL syntax error at alu_control.vhd(32) near text "Funct"; expecting "(", or "'", or "."  This error repeats for every elseif line I have written.

[Altera_Forum]

ummmm no? I dont see what your reply is referring to...

[Altera_Forum]

sorry got your post mixed up with something else. Line32 is the line with the first if?

[Altera_Forum]

`For clarity (please do this the next time you post code as well) 

This is how your code now looks?library ieee ; use ieee.std_logic_1164.all; use ieee.std_logic_unsigned.all; --------------------------------------------------- entity alu_control is port( ALUOp: in std_logic_vector(1 downto 0); Funct: in std_logic_vector(5 downto 0); ALUCtrl: out std_logic_vector(3 downto 0) ); end entity alu_control; ---------------------------------------------------- architecture alu_control_arch of alu_control is begin process (ALUOp, Funct, ALUCtrl) begin case ALUOp is when "00" => if Funct = "xxxxxx" then ALUCtrl <= "0010"; end if; when "01" => if Funct = "xxxxxx" then ALUCtrl <= "0110"; end if; when "10" => if Funct = "100000" then ALUCtrl <= "0010"; elsif Funct = "100010" then ALUCtrl <= "0110"; elsif Funct = "100100" then ALUCtrl <= "0000"; elsif Funct = "100101" then ALUCtrl <= "0001"; elsif Funct = "101010" then ALUCtrl <= "0111"; else ALUCtr <= "xxxx"; end if; when others => ALUCtrl <= "xxxx"; end case; end process; end architecture alu_control_arch;

[Altera_Forum]

i apoligize for the sloppy code entry, wasnt sure how to format on this site. 

Line 32 is the forst of the else if statements. The error I gave is shown for the ELSEIF statements at 34 36 and 38.

[Altera_Forum]

TO_BE_DONE

[Altera_Forum]

OMG I JUST REALIZED WHAT IT WAS. I FEEL SO STUPID HAHAHA 

I was writing elsEif instead of elsif......is there a facepalm emoji on here anywhere???  This was too obvious and a very rookie mistake on my part. Thanks for all your help and input so far! I am currently working out any new errors. Will report back on anything new.

[Altera_Forum]

The compiler seems to not like ALUCtrl in the sensitivity list since it is of type out, but without it the compiler infers latches, plus a couple of warnings. 

Warning (10631): VHDL Process Statement warning at alu_control.vhd(20): inferring latch(es) for signal or variable "ALUCtrl", which holds its previous value in one or more paths through the process Warning: Latch ALUCtrl$latch has unsafe behavior Warning: Ports D and ENA on the latch are fed by the same signal Funct Warning: Latch ALUCtrl$latch has unsafe behavior Warning: Ports D and ENA on the latch are fed by the same signal Funct Warning: Latch ALUCtrl$latch has unsafe behavior Warning: Ports D and ENA on the latch are fed by the same signal Funct   All other warnings are simply pin assignment warnings.  Is there any way to avoid these potential errors?

[Altera_Forum]

There are several problems with your code: 

1. Latch inference. All signals assigned in the process should be assigned in EVERY BRANCH to avoid infering latches (unless it is a synchronous process). This means assigning '0' or '1'. Assigning 'X' does not map to real hardware   2. Assigning to 'X' is not dont care - it is unknown. You should not be assigning signals to 'X' or checking a signal for 'X' in synthesisable code. You are very likely to get differences in simulated and real behaviour.