about vhdl code for cic interpolation filter

[Altera_Forum]

i am attaching one pdf file based on cic filter.In the bitgrowth section the author has mentioned about the increase in the bits at the output stage .Suppose if i am writing a vhdl code for cic interpolation stage for example let differential delay M=1, Interpolation factor R=8,Input bit size be 23 and number of comb sections and integrator sections be N=9.Then how the output bit size change for each comb section.Can anybody explain me with the above mentioned parameters?

[Altera_Forum]

--- Quote Start ---  I guess you are talking about functional simulation resuts? The uninitialized register ifilterout32 is propagating to the last integrator stage.  You need to initialize all register variables in functional simulation.  --- Quote End ---    Is the initialization that i have done in the given code is not enough?

[Altera_Forum]

You are right, I didn't look thoroughly at the code. In this case, I expect that "undefined" is propagating from din. You'll need to look at the exact waveforms for each register to identify where undefines comes from, ore use a respective trace function in Modelsim. 

 I also noticed that it's apparently a Xilinx project. This is not the right forum to get help for possible problems with Xilinx tools.