auto gated clock conversion help

[Altera_Forum]

I am trying to implement some ASIC code in an FPGA, and unfortunately the code has gated clocks. Because of the huge clock skew problems this causes I was hoping to use the Auto Gated Clock Conversion option to create clock enables instead of the clock gating. I have turned on this option in Quartus II and it didn't seem to do anything. As far as I can tell no gated clocks were converted to clock enables. I tried checking the report on gated clock conversion that is supposed to show up under the Optimization Results of the Analysis & Synthesis Report and it's not there either. I just get the feeling the setting is being ignored, but I don't know why. Has anyone used this successfully before? 

 Just as some background I have the gated clock as a small module that is coded as Altera suggests:   output clk; // clock output  input en; // clock enable  input eclk; // early clock   reg en_q; // latched enable   always@(negedge eclk)  begin  en_q <= en;  end   assign clk = eclk && en_q;  I also have the eclk created in an sdc file like this (it's the output of a PLL):# input clock create_clock -period 10 clk_in# generate all clocks from PLL (including eclk) derive_pll_clocks -create_base_clocks  Is there something obvious that I'm missing? Any help would be appreciated. Thanks!

[Altera_Forum]

Why have the gated clock at all? It looks like it's just turning it on and off every other clock cycle. If that's the case, just have the PLL create a clock that's half that rate. 

 A secondary thing that's pretty straightforward is to instantate the altclkctrl block, which is basically the global driver used between the PLL and global clock tree(this block is always in the design, just inferred if you don't manually enter it). It has an enable signal, which you could drive en_q into(as an enable is basically the same thing as an AND gate).  Don't know why the auto gated clock conversion isn't working, but I think either of those should work.

[Altera_Forum]

The example code is just the clock gating module (which is instantiated hundreds of times in the ASIC code). The actual en signal input has various logic on it depending on the instance, so it's unfortunately not simply turning the clock on and off each clock cycle. 

 I would simply instantiate the altclkctrl block, but as I mentioned this module is in the code hundreds of times. Not only would it be quite painful to replace each instance, I don't think there will be enough clocking resources in the FPGA. Can I create several hundred altclkctrl blocks? I guess if that's possible it's at least an option.  What I really wanted to do was switch all the gated clocks to clock enables. That's why I'm asking about the auto gated clock conversion. The problem is that when I turn it on nothing seems to happen. I'm not sure if there is some conflict with another constraint I've set or what.

[Altera_Forum]

Yep, my solutions are useless for you. (There are not enough altclkctrl blocks). I would take a small subsection of real code(at least that has real clock enables) and file an SR on it, so an Altera engineer can look at it and hopefully direct to what's wrong.

[Altera_Forum]

Thanks for your help and advice, Rysc. 

 Does anyone out there know if there are any tricks to using the Auto Gated Clock Conversion option? Any help would be appreciated. Thanks!

[Altera_Forum]

--- Quote Start ---  Thanks for your help and advice, Rysc.  Does anyone out there know if there are any tricks to using the Auto Gated Clock Conversion option? Any help would be appreciated. Thanks!  --- Quote End ---    Hi, Did you get any solution for this issue? I'm facing the same problem in my design.  Thanks, Gopal

[Altera_Forum]

--- Quote Start ---  Thanks for your help and advice, Rysc.  Does anyone out there know if there are any tricks to using the Auto Gated Clock Conversion option? Any help would be appreciated. Thanks!  --- Quote End ---    Hi,   the Quartus "gate clock conversion" will only work if there are only, and, or, xor gates in the control of the clock gating. Maybe your Latch is the problem. Try to describe your gating only with gates. What kind of clock gating are you doing? Are the clocks only switched off in order to save power or do you clock dividing ? Has every clock gating cell different control signals or are there groups which uses the  same signals ? If yes, you can at least reduce the number of gating cells.  Kind regards  GPK

[Altera_Forum]

--- Quote Start ---  Hi,   the Quartus "gate clock conversion" will only work if there are only, and, or, xor gates in the control of the clock gating. Maybe your Latch is the problem. Try to describe your gating only with gates. What kind of clock gating are you doing? Are the clocks only switched off in order to save power or do you clock dividing ? Has every clock gating cell different control signals or are there groups which uses the  same signals ? If yes, you can at least reduce the number of gating cells.  Kind regards  GPK  --- Quote End ---    Hello Pletz,  We are switching off the clocks to save power. This is an ASIC design which we are trying to run on FPGA.  I've taken your example from another post  http://www.alteraforum.com/forum/showpost.php?p=15216&postcount=4  Even here the clock gating is not converted into register enable nor anything goes into the report.  Thanks, Gopal

[Altera_Forum]

--- Quote Start ---  Hello Pletz,  We are switching off the clocks to save power. This is an ASIC design which we are trying to run on FPGA.  I've taken your example from another post  http://www.alteraforum.com/forum/showpost.php?p=15216&postcount=4  Even here the clock gating is not converted into register enable nor anything goes into the report.  Thanks, Gopal  --- Quote End ---    Hi,  is the clock gating still necessary on the FPGA ?  I have a small project attached. The clock conversion takes place only:  1. You have switch on the clock conversion under   "Assignments" -> "Settings"-> "Analysis & Synthesis Settings" -> "more Settings"   Auto Gated Clock Conversion ON  2. You have to use TimeQuest as Timing Analyzer  3. You have to define your clocks in TimeQuest    Kind regards  GPK

[Altera_Forum]

The problem that I was having was directly related to using the PLL inside the high-speed transceivers. Apparently there was a bug in Quartus where derive_pll_clocks didn't work correctly in synthesis. The solution for me was to run all the way through fitter. Then write out an SDC file in TimeQuest to get the full name of the PLL clock output. Put the clock information back in my input SDC file using the create_clock command (replacing the derive_pll_clocks). At this point the clocks were all created correctly and I was able to synthesize again with the Auto Gated Clock conversion turned on. 

 I don't know if they've fixed this bug in the latest Quartus 10.0 or not. Hope this helps.

[Altera_Forum]

Hi, 

 I am trying to understand how does the automatic clock gating conversion option affect the synthesized design. As an example, I tried the clock gating conversion with the following example code : - module clock_gating_conversion_project( input CLOCK_50, output reg counter_1, output reg counter_2 ); always@(posedge CLOCK_50) begin counter_1 <= counter_1 + 1; end wire gated_clock; clock_gate clock_gate_1( .clkout (gated_clock), .clk (CLOCK_50), .en (counter_1), .ti (2'b0)); always@(posedge gated_clock) counter_2 <= counter_2 + 1; endmodule  The "clock_gate" module is a simple AND gate.   I turned the "Auto Gated Clock Conversion" option "On" in the "Advanced Settings (Synthesis)" tab.  However, I tried the synthesis without defining the clock "CLOCK_50" in the .sdc file using the create_clock statement. In spite of this, Quartus identified that CLOCK_50 was a clock signal getting gated and performed clock gating conversion (I concluded this by seeing that the clocks going to all registers in the post-fitting schematic were free running, and enable signals were used for each flop).  To see what would happen if I define the CLOCK_50 signal as a clock in the .sdc file, I added the following statement to the .sdc file : - create_clock -period 20.000 -name CLOCK_50   I re-ran the compilation process with the the Auto Gaed Clock Conversion option turned On, and saw that Quartus had performed the clock gating conversion in this case as well, as expected. However, i saw that the (post-fitting) schematics were different, meaning that the compilation process was not exactly the same.  I think I should consider the compilation with the explicit create_clock constraint as the correct one, but am wondering :-  1) Is the compilation done by Quartus without the explicit create_clock constraint correct as well? It seems to have done some clock gating conversion as the clocks going to all registers are free running with enable signals being used, and  2) Why did Quartus perform the clock gating conversion in the above case, in the absence of the clock definition in the .sdc file, even though the create_clock constraint is supposed to be necessary to perform the conversion?  Any advice would be helpful to make me understand this. Thanks a lot!  Regards, Akshay