bitwrite memory model for altera FPGAs

Altera_Forum · ‎10-04-2015

hi,

i know how to make generic byte write, word write memory models in verilog for FPGAs. but is there any way of making a bit write memory model for altera FPGAs?

i have looked online quite a lot but couldn't find one. and the memory model i am making ends up having a couple of cycles of delay in reads and write (because of the bit-write nature). so if someone has worked with bitwrite memory models or knows where to find generic code for them (online link), that would be great.

thanks in advacne for the help.

z.

Altera_Forum · ‎10-06-2015

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i know how to make generic byte write, word write memory models in verilog

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Post some examples of your code and I suspect we can help with code consistent with what you have already.

Cheers,

Alex

Altera_Forum · ‎10-09-2015

i guess i've managed a work-around for now - used the alteraIP and generated a memory block and instantiated it 8 times. and in each instance, i write just 1 bit (using the wren signal of the block). it is an expensive way of doing things but at least it wont induce 2 - 3 cycle delay (or more) if i try and code the memory model myself. esp. because in my functional sim, i cant have more than 1 cycle delay in the reads/writes.

thanks.

z.