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Altera_Forum
Honored Contributor I
2,227 Views

combinational loops as latches

I got a warning: TimeQuest Timing Analyzer is analyzing 24 combinational loops as latches. I was told this was caused by incomplete output changes corresponding to the input changes. That is, some input changes were not reflected in the output. I do ignore some input changes due to the design. Except this, I couldn't see any other problems. Any ideas how to take care of the situation? Can I simply ignore the warning?

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16 Replies
Altera_Forum
Honored Contributor I
287 Views

I think u got value to the comb logic which feedback to its input, this ia bad design, because timing analyzer cannot analyze the comb logic path properly. If the loopback is not latency sensitive, try to register the output value before you loop back

Altera_Forum
Honored Contributor I
287 Views

Thanks for all your help. However, I have checked very carefully, and, actually, I use "<=" instead of "=" whenever I could (I have used many always blocks for the updates). Besides, I use intermediate variables (wire types) outsides the always loops for the calculations before the next rising edge of the clock so that the registers' input values could be updated quickly at the posedge of clock. I really couldn't see any pure combinational loops. Is there a way the tool could tell me what the combinational loops are corresponding to the warning? This warning is very brief and doesn't have any specific details. Thanks

Altera_Forum
Honored Contributor I
287 Views

I dint really understand your code in "words" :) 

but you may try to use Design Assistant, but it might dump similar message. 

Try to right click on the error message, and locate to the design file
Altera_Forum
Honored Contributor I
287 Views

 

--- Quote Start ---  

This warning is very brief and doesn't have any specific details. 

--- Quote End ---  

 

Unlikely, it shows all latch instances in your design below the warning, if you unfold it. 

 

Not all latches can be avoided, some are introduced by Quartus, e.g. the previously discussed "equivalent circuit" for asynchronously loaded registers.
Altera_Forum
Honored Contributor I
287 Views

 

--- Quote Start ---  

Unlikely, it shows all latch instances in your design below the warning, if you unfold it. 

 

Not all latches can be avoided, some are introduced by Quartus, e.g. the previously discussed "equivalent circuit" for asynchronously loaded registers. 

--- Quote End ---  

 

 

I got about 40 sub-warnings for this "equivalent circuit " problem when I unfold this "equivalent circuit " warning.  

 

What if I simply ignore this "combinational loops as latches" problem? I know this could affect the timing analysis, but what could be the worst situation that would happen?
Altera_Forum
Honored Contributor I
287 Views

 

--- Quote Start ---  

I got about 40 sub-warnings for this "equivalent circuit " problem when I unfold this "equivalent circuit " warning. 

--- Quote End ---  

 

So you know there 40 latch instances. Why don't you try to trace some of them? Double-clicking the warnings should give a first hint.
Altera_Forum
Honored Contributor I
287 Views

all the latch instances for "equivalent circuit" warning comes from  

 

always @(posedge clk or posedge reset) begin 

if(reset) begin: OVER_LOOP 

... ; 

end else if (clk) begin 

... ; 

end // end of if OVER_LOOP 

 

end // end of always 

 

When I double click all 42 expanded warnings, it goes to the same statement "end else if (clk) begin". 

 

However, for the warning "TimeQuest Timing Analyzer is analyzing 24 combinational loops as latches", when I double click it, there is no highlighted line in the text field (.v file).
Altera_Forum
Honored Contributor I
287 Views

You possibly have a multiple bit asynchronous load under the reset condition? 

 

Generally, I can't say if Quartus is always showing the code generating the latch, but it mostly works for me.
Altera_Forum
Honored Contributor I
287 Views

For the latches introduced by Quartus, it should be due to the optimization done by the Quartus to replace some circuit, I believe you can turn off the optimization through the Quartus -> assignment -> setting 

 

But I still doubt the optimization introduce the warnings. 

 

Ignore this warning might cost you more time to debug in future in the hardware, as you might see some behavior not match your expectation, and you will have difficult during debugging
Altera_Forum
Honored Contributor I
287 Views

 

--- Quote Start ---  

You possibly have a multiple bit asynchronous load under the reset condition? 

 

Generally, I can't say if Quartus is always showing the code generating the latch, but it mostly works for me. 

--- Quote End ---  

 

 

Here is what I have for the reset block: 

 

Accu_Phi_in <= 12'b000001010111;  

Accu_Phi_inm <= 12'b111110101001;  

L <= 3'b000;  

Iplus <= {Iplusin[WIDTH-1],Iplusin[WIDTH-1:0]}; 

Qplus <= {Qplusin[WIDTH-1],Qplusin[WIDTH-1:0]}; 

Iminus <= {Iminusin[WIDTH-1],Iminusin[WIDTH-1:0]}; 

Qminus <= {Qminusin[WIDTH-1],Qminusin[WIDTH-1:0]}; 

 

All the variables on the left are register variables, and on the right are inputs to this submodule or some constants. This is for the initialization for the calculation of a new group of input data. The timing is controlled by the clocks (reset, clk). Is this something related to "multiple bit asynchronous load"? 

 

Besides, one warning for each bit for the four variables (Iplus, Qplus, Iminus, Qminus) --- 52 warnings, which says each bit is converted into an equivalent circuit using its corresponding register.
Altera_Forum
Honored Contributor I
287 Views

 

--- Quote Start ---  

For the latches introduced by Quartus, it should be due to the optimization done by the Quartus to replace some circuit, I believe you can turn off the optimization through the Quartus -> assignment -> setting 

 

But I still doubt the optimization introduce the warnings. 

 

Ignore this warning might cost you more time to debug in future in the hardware, as you might see some behavior not match your expectation, and you will have difficult during debugging 

--- Quote End ---  

 

 

The setting for "Analysis and synthesis" is: "balanced", "Power-up don't care", and "Normal compilation". So based on all the info I posted here, can somebody figure out how to fix all these 52 warnings? That is, one bit of each 13 bits' register (totally 4 registers) has a "converting to equivalent circuit" warning.
Altera_Forum
Honored Contributor I
287 Views

 

--- Quote Start ---  

All the variables on the left are register variables, and on the right are inputs to this submodule or some constants. This is for the initialization for the calculation of a new group of input data. The timing is controlled by the clocks (reset, clk). Is this something related to "multiple bit asynchronous load"? 

 

Besides, one warning for each bit for the four variables (Iplus, Qplus, Iminus, Qminus) --- 52 warnings, which says each bit is converted into an equivalent circuit using its corresponding register. 

--- Quote End ---  

 

That's a nice example of asynchronous load, so the warnings are pretty understandable. But why at all are you performing an asynchronous reset? Isn't the "initialization for the calculation of a new group of input data" executed as part of the synchronous design sequence? 

 

I presume you know, that the reset signal must be released synchronous to clock edge, otherwise it won't load the intended values reliably.
Altera_Forum
Honored Contributor I
287 Views

Yes, I considered the timing for this reset and clock signals. 1. I need this reset signal to be effective before the rising edge of clock comes (e.g. occurs at the falling edge of clock of previous clock cycle). At the same time, I need this reset signal to be slower than the clock signal (e.g. 8 times slower). I am sorry that I am new on this part. Any advise on how to fix this problem? Any tutorial on the asynchronous and synchronous design? 

 

I did such a design because I need 8 loops of calculation for each group of input data. Then the iteration needs to be reset with some new inputs for another round of calculation (8 loops again). Therefore, I use "clock" to control the loops and "reset" to control the update of the input data. 

 

Please do advise on how to fix the problem and any related tutorial. Thanks in advance.
Altera_Forum
Honored Contributor I
287 Views

Again, seek solutions for the above problem in this thread...  

 

Thanks in advance!
Altera_Forum
Honored Contributor I
287 Views

I cant really see any loop here... 

the right side you mention is input to the submodule, is it input from top level, or where are they from
Altera_Forum
Honored Contributor I
287 Views

The loops are clicked by the rising edge in the else block. Yes, it is from the top level. 

 

However, I simply decided to use synchronous bit loading, which has eliminated all the latches. Thanks.
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