executable file

[Altera_Forum]

Hi guys, 

  I am wondering does there exists an executable file in Quartus II project that can be ran independent of the Quartus software environment?Thanks.

[Altera_Forum]

There are lots of different stand-alone executables. 

 What feature were you looking to use?  Cheers, Dave

[Altera_Forum]

Hi Dave, 

  I have done a project under Qaurtus II. Now I intend to let others to test it. So I am wondering is it possible to make the project as an executable file and then let others do some tests on it? Thanks.

[Altera_Forum]

--- Quote Start ---    I have done a project under Qaurtus II. Now I intend to let others to test it. So I am wondering is it possible to make the project as an executable file and then let others do some tests on it?  --- Quote End ---    You need to be a little clearer on what you mean by 'executable'.  You can create a synthesis script or makefile that will allow others to build your design from source files. Is that what you are looking for?  Is your design straight VHDL or Verilog, does it use SOPC Builder or Qsys, and does it contain a NIOS II processor and application code?  Cheers, Dave

[Altera_Forum]

Hi Dave, 

  'executable' is similar as '.exe' file for C compiler. It allows others to run and test its functionality, but they cannot see the C code inside. I have no idea if there is a similar '.exe' file for Quartus, so I can let others to test it, but nobody could see the exact code and schematic inside. By the way, my project is implemented in schematic(basic gates). Thanks.

[Altera_Forum]

--- Quote Start ---    'executable' is similar as '.exe' file for C compiler. It allows others to run and test its functionality, but they cannot see the C code inside.    --- Quote End ---     The analogy for an FPGA is the programming file or .sof file for the FPGA.    --- Quote Start ---    I have no idea if there is a similar '.exe' file for Quartus, so I can let others to test it, but nobody could see the exact code and schematic inside. By the way, my project is implemented in schematic(basic gates). Thanks.  --- Quote End ---    There's two things you can do; provide the output netlist in Verilog or VHDL format (.vo or .vho file) to allow people to simulate the design, and provide the .sof file. However, the .sof file is specific to a particular FPGA or board.  There must be a way to encrypt designs too. I have never needed to use that, so cannot help. Personally, I prefer to let people see the source code.  Cheers, Dave

[Altera_Forum]

Dave, thank you! I need to find a way to encrypt it.