need help to design calculator function (addition and multiplication)

[Altera_Forum]

i need to design calculator that performs operations of addition and multiplication of 2 input (5-bit binary) that representing signed decimal numbers (range, -16 to + 15). I've already done the coding but now i'm stuck in BCD and seven segment coding..can anybody help me :cry: 

 module calculator (a,b,outadd,outmul, add,mul,clk);   input signed [4:0] a ;  input signed [4:0] b;  input add , mul;   input clk;  output reg [5:0] outadd;  output reg [9:0] outmul;    always @ (posedge clk)  begin  if (add)  outadd <= a + b;  begin  if (mul)  outmul <= a * b;    end  end  endmodule

[Altera_Forum]

hi,hamema. 

 I will tell you two things. one is 7segLED. see attached file. a means LED's 0 pin b means LED's 1 pin   .... g means LED's 6 pin the dot means LED's 7 pin  the second thing is... just use case sentence. when you get value "0" set each pin like that. ------------------ verilog HDL logic ------------------- case ( outadd ) 0: begin  a = 0;//(negative logic )  b = 0;  c = 0;  d = 0;  e = 0;  f = 0;  g = 1;  dot = 1; //whatever end 1: begin  a = 1; .... endcase -----------------------------------------------------------  do you get what I say?

[Altera_Forum]

Thanks akira, 

 Did I still need to put BCD coding in this program? Can you help me to check the either my program is correct or not...Thanks again :)  module calculator (x,y,outadd,outmul, add,mul,clk,a,b,c,d,e,f,g,dot);   input signed [4:0] x, y ;   input add , mul;   input clk;  output reg [5:0] outadd;   output reg [9:0] outmul;  output reg [4:0] a,b,c,d,e,f,g,dot;   always @ (posedge clk)  begin  if (add)  outadd <= x + y;  case ( outadd )  0:  begin  a = 0;   b = 0;  c = 0;  d = 0;  e = 0;  f = 0;  g = 1;  dot = 1;   end  1:  begin  a = 1;   b = 1;  c = 1;  d = 1;  e = 1;  f = 1;  g = 0;  dot = 0;   end  endcase   begin  if (mul)  outmul <= x * y;  case ( mul )  0:  begin  a = 0;   b = 0;  c = 0;  d = 0;  e = 0;  f = 0;  g = 1;  dot = 1;   end  1:  begin  a = 1;   b = 1;  c = 1;  d = 1;  e = 1;  f = 1;  g = 0;  end  endcase end end  endmodule

[Altera_Forum]

*case(outmul)

[Altera_Forum]

The result of your multiply operation needs a 3 decimal digits representation. I guess, you don't want to create a table (or case structure) with 511 entries for all 21 segments? 

 So you would want to implement a signed binary to BCD to decoder and then apply 7-segment decoding to each digit. I further guess, that you won't be assigned to a complex exercise without some previous lectures dealing with the involved mathematical operations or at least respective literature links.  My suggestion is to try the decoding by pencil and paper first and than think about a Verilog HDL representation.

[Altera_Forum]

It's incorrect module instantiating syntax, I think. You made the BCD decoding more complicated than necessary. Hopefully the design compiler will drop redundant calculations. 

 Finally, negative numbers aren't handled correctly, I fear. The BCD decoder doesn't work for 2s complement, negative numbers have to be converted to sign/magnitude first. You have to consider how to display the sign, by the way.

[Altera_Forum]

right now i really confuse and doesn't know what to do... :cry:

[Altera_Forum]

A simple numerical example: 

-10 * 15 = -150 in signed binary you get 10110 * 01111 = 1101101010  to convert to BCD, you would invert negative numbers first +150 0010010110 then apply BCD decoding 150/100 = 1 150/10%10 = 5 150%10 = 0

[Altera_Forum]

Thanks FvM, but i can't compile due to syntax error-expecting error at always @(*)....

[Altera_Forum]

--- Quote Start ---  but i can't compile due to syntax error  --- Quote End ---   Which code you are referring to? In your previously posted code, the module instantiation syntax has been wrong, missing the module name. <module_name> <inst_name>(<port_connects>);

[Altera_Forum]

....... 

begin  if (mul)  begin  outmul <= x * y;  end  always @* --------------//syntax error...next 'always' expecting 'end'  begin  bcd_1 = outmul/100;  bcd_2 = outmul/10%10;  bcd_3 = outmul%10;  end  sevsegment_1 (bcd_1,out1);  sevsegment_2 (bcd_2,out2);  sevsegment_3 (bcd_3,out3);  end  end endmodule

[Altera_Forum]

Where is the module name? 

sevsegment_1 (bcd_1,out1);should be 7segment sevsegment_1 (bcd_1,out1);

[Altera_Forum]

got problem when i want to adding in negative side at bcd...example -16-16 =-32, in bcd the answer is 992...why this thing happen...

[Altera_Forum]

I have told before, how negative numbers can be treated. You can't apply BCD conversion to 2s complement number representation.

[Altera_Forum]

I already invert the negative using this coding, but the answer still same 

 always @ (*) begin if (resulta[9]==0) inv=resulta;  else if (resulta[9]==1) inv = ((~resulta)+5'b00001);

[Altera_Forum]

--- Quote Start ---  I already invert the negative using this coding, but the answer still same  --- Quote End ---    Effectively impossible in my opinion.

[Altera_Forum]

why?:confused:

[Altera_Forum]

You are right akira. I am also agreed with your process.