negative edge trigger

[Altera_Forum]

hi guys , i need a little help here. 

i need to create a negative edge trigger for a period of one clock only. meaning the signal was at '1' and went down to '0' for one clock period. does anyone have an idea how to do it in VHDL ?

[Altera_Forum]

to do a negative edge trigger - you flop the signal twice and then AND the second flop with the NOT of the first flop ex: 

 signal q: std_logic; signal qq : std_logic; signal neg_edge_trig : std_logic;   process(clk) begin if rising_edge(clk) then q <= input_signal; qq <= q; end if; end process;   neg_edge_trig <= NOT q AND qq;

[Altera_Forum]

will it preform it for exact one clock period ?? 

p.s. thank you very much for the replay.

[Altera_Forum]

also wonder , if i want to make it automatically. should i switch the 'input_signal' by '1' ?

[Altera_Forum]

Yes this will create a 1 cycle pulse following the falling edge of your input signal

[Altera_Forum]

--- Quote Start ---  to do a negative edge trigger - you flop the signal twice and then AND the second flop with the NOT of the first flop ex:   signal q: std_logic; signal qq : std_logic; signal neg_edge_trig : std_logic;   process(clk) begin if rising_edge(clk) then q <= input_signal; qq <= q; end if; end process;   neg_edge_trig <= not q and qq;  --- Quote End ---    By this way, neg_edge_trig is a result of combinational logic (= not a registered signal).