question about writing testbench

Altera_Forum · ‎05-27-2012

Hi all,

I wrote a testbench for a full adder. However, the testbench doesnt work. The function of the testbench is, that it tries to read input stimulis from a file called fa_in.txt and output results to a file called fa_out.txt. The error is, that entity fa wrote nothing to output file fa_out.txt, and there is no any waveform in Modelsim editor. The input file looks like:

----file begins----

000

001

010

011

100

101

110

111

----file ends----

after simulation, the output file should looks like:

---file begins----

1.000---->00

2.001---->01

3.010---->01

4.011---->10

5.100---->01

6.101---->10

7.110---->10

8.111---->11

---file ends----

Can anybody shed some light on my code? Thanks.

----VHDL code for full adder----

library IEEE;

use IEEE.STD_LOGIC_1164.all;

entity fa is

port( CIN,A,B:in BIT;

COUT,SUM: out BIT);

end fa;

architecture fa_behavior of fa is

begin

process(CIN,A,B

variable TEMP_COUT,TEMP_SUM:BIT;

begin

case CIN&A&B is

when "000" =>TEMP_COUT:='0';TEMP_SUM:='0';

when "001" =>TEMP_COUT:='0';TEMP_SUM:='1';

when "010" =>TEMP_COUT:='0';TEMP_SUM:='1';

when "011" =>TEMP_COUT:='1';TEMP_SUM:='0';

when "100" =>TEMP_COUT:='0';TEMP_SUM:='1';

when "101" =>TEMP_COUT:='1';TEMP_SUM:='0';

when "110" =>TEMP_COUT:='1';TEMP_SUM:='0';

when "111" =>TEMP_COUT:='1';TEMP_SUM:='1';

end case;

COUT<=TEMP_COUT;SUM<=TEMP_SUM;

end process;

end fa_behavior;

----VHDL code ends----

----testbench code----

library IEEE;

use IEEE.STD_LOGIC_1164.ALL;

use STD.TEXTIO.all;

entity TB_fa is end;

architecture IO_EXAMPLE of TB_fa is

component fa

port (CIN,A,B:in BIT;COUT,SUM: out BIT);

end component;

file VEC_FILE:TEXT

open READ_MODE is "c:/fa/fa_in.txt";

file RESULT_FILE:TEXT

open WRITE_MODE is "c:/fa/fa_out.txt";

signal S: BIT_VECTOR(0 to 2);

signal Q: BIT_VECTOR(0 to 1);

begin

TB_fa: fa port map (S(0),S(1),S(2),Q(0),Q(1));

process

constant PROPAGATION_DELAY:TIME:= 2 ns;

variable BUF_IN,BUF_OUT:LINE;

variable OUT_STR:BIT_VECTOR(0 to 1);

variable NUM_VECTORS:INTEGER:=0;

variable VAR_S:BIT_VECTOR(0 to 2);

begin

while not ENDFILE (VEC_FILE) loop

READLINE(VEC_FILE,BUF_IN);

assert(BUF_IN'LENGTH=3)

report "Vector does not have three bits"

severity ERROR;

READ(BUF_IN,VAR_S);

S<=VAR_S;

wait for PROPAGATION_DELAY;

NUM_VECTORS:=NUM_VECTORS+1;

WRITE(BUF_OUT,NUM_VECTORS);

WRITE(BUF_OUT,STRING'("."));

WRITE(BUF_OUT,S);

WRITE(BUF_OUT,STRING'("---->"));

OUT_STR:=Q;

WRITE(BUF_OUT,OUT_STR);

WRITELINE(RESULT_FILE,BUF_OUT);

end loop;

report "Completed processing all vectors.";

wait;

end process;

end IO_EXAMPLE;

----testbench code ends----

Altera_Forum · ‎05-28-2012

you didnt say what the error is.

But I would suggest having separate processes for input and output.

Altera_Forum · ‎05-28-2012

--- Quote Start ---

you didnt say what the error is.

But I would suggest having separate processes for input and output.

--- Quote End ---

Hi,

The error is, that the full adder entity didnt write anything to output file fa_out.txt, and there is no any waveforms in Modelsim editor.

Altera_Forum · ‎05-28-2012

once you fix the syntax error, it works perfectly fine for me.