.sdc file help: 50MHz input, 2 PLLs, some state machines and some custom code

Altera_Forum · ‎07-08-2013

Hello people.

Getting some timing constraint errors without having created an sdc file I could use some help.

First off all I would like not to spend much time reading the lengthy manual of ALTERA but only some commands for the sdc file.

What would the basic commands be for a DE0 Nano project with:

a 50MHz input clock

an ALTPLL with 2 outputs at 450MHz and 75MHz

some state machines and some custom code.

I know I should put some clock constraints, derive PLLs and derive clock unceertainties but what would be the final sdc file?

Anybody has an idea??

Altera_Forum · ‎07-09-2013

Sometimes it is necessary to read through the endless documents of Altera. It is a tedious job but it will pay off.

A first thing to do is to constraint your input and output clocks. So if you have an input clock of 50 Mhz (ie period is 20ns) the constraint command in the sdc file will be:

1. create_clock -name board_clk -period 20.000 -waveform { 0.000 10.000 } [get_ports {CLK}] //CLK will be whatever name you gave to the clock port in your top design

To constraint your PLL there is basically three approaches. The easiest would be to implement an automatic constraint for both input and output clocks. For this you need:

2. derive_pll_clocks

Now, as long as your custom code doesn't contain other cores such as transceivers, clock muxes, clock muxes with enables.. etc, you don't need to do anything (if I am correct) as far as timing is concerned. However in some cases if you have output/input pins operating at high clock freq then you will need to perform input/output constraint commands at a further stage.

Good to add

3. derive_clock_uncertainty

Also don't forget to start your sdc file with setting your time format:

4. set_time_format -unit ns -decimal_places 3

I hope this will give the quick necessary to start working

Altera_Forum · ‎07-10-2013

Thanks a lot for the answer. I think I have done this basic stuff but I am still not meeting the time requirements. How do I setup my files so that the compiling and fitting is done to avoid any timing problems. In timequest I can see that I have negative slack for some paths.