simulation error

Altera_Forum · ‎09-10-2012

I have a working legacy vhdl project that I can compile and simulate in Modelsim. I needed to add an empty output signal to a fifo that instantiated in the design. The original Megawizard-generated code was in Quartus 5.1. The latest Quartus version that was used to compile design is 6.1, so I regenerated the fifo in 6.1. I updated the instantiation and component declaration (I just connected the new empty flag to open for early testing), but now I can't simulate the design anymore. It compiles, but during vsim execution, Modelsim indicates following error:

# ** Error: tb_top.vhd(1337): Bad default binding for component instance "dut : scan_conv".# (Component port "temp_scl" is not on the entity.)# ** Warning: [1] tb_top.vhd(1337): (vopt-3473) Component instance "dut : scan_conv" is not bound.

The temp_scl signal is last signal on entity list of top-level of design. I've verified all the I/O matches up between entity and the instance in the test bench, so don't know what is causing this. It acts as if part of the design has been optimized out and stripped out some of the signals.

Regards, Grady

Altera_Forum · ‎09-11-2012

how do you compile and simulate in modelsim? you got to point the modelsim vlog to your updated megafunction vhdl file to compile first.

Altera_Forum · ‎09-11-2012

I compile using a do file script that has a series of vcom commands. These compile the fifo megawizard-generated file (wxr_fifo.vhd) into dut_lib modelsim library. The file that instantiates it (wxr_output.vhd) is also compiled into dut_lib along with all synthesizable source. The testbench top-level (tb_top.vhd) is compiled into work library. The script that invokes the simulator uses work folder (calls vsim work.tb_top ...).

(1.) I tried inserting the following library statements in wxr_output.vhd:

library dut_lib;

use dut_lib.all;

but still get vsim error.

(2.) I tried deleting all compiled modelsim folders & recompiling, but get same error.

(3.) Current Modelsim version is 6.5e on Linux. Tried recompiling everything, including modelsim libraries in version 10.1a & simulating, but get same error.

Note that I have BindAtCompile=0 so default binding is done at load time (the compile script that calls out the hundreds of files to compile doesn't do it in bottom-up order).

Also, the original fifo was compiled in Quartus 5.1. The regenerated code in 6.1.

Altera_Forum · ‎09-12-2012

Got it working. Looks like bit was dropped during prior copy of design. Recopied it, made same change, now it simulates OK. GMM