std_logic_vector and std_logic - Intel Community

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std_logic_vector and std_logic

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I'm using Mega Wizard Manager of Quartus to create ram with one bit data, so input and output are defined as std_logic_vector(0 downto 0);

but when I open ModelSim to simulate my project, it refuse this declaration "0 downto 0" and return an error.

Anyone can solve this problem, please?

thanks in advance.

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The same problem:

http://www.alteraforum.com/forum/showthread.php?t=23213

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