the connection of multiple modules

Altera_Forum · ‎05-16-2016

module LED(clk_div320k,rst,out,common1,common2,common3,common4,BCD_hunds,BCD_tens,BCD_units);

input clk_div320k,rst,BCD_hunds,BCD_tens,BCD_units;

output reg [6:0]out;

output reg common1,common2,common3,common4;

reg [1:0] state , next_state;

parameter s1=2'b01,s2=2'b01,s3=2'b10,s4=2'b11;

divide_320k h1(.clk_div320k(clk_div320k),.rst(rst));

Binary_turn_BCD h2(.BCD_hunds(BCD_hunds),.BCD_tens(BCD_tens),.BCD_units(BCD_units));

I want to know how to combine two modules by a parallel method(like A->B->C)

I think I use the wrong way , like A(B)or B(C)

the compilation result has two types,

if I ignore the red program , it tells me cannot be assign more than one value

and if i ignore blue program, the compilation will be success , but there will be a lot of warming

below this program is state machine, but i think the fault is not in the state machine

sorry my english is not pretty good

----------------------------

always@(posedge clk_div320k)

begin

if(rst)

state <= s1;

else

state <= next_state;

end

always@(*)

begin

case(state)

s1:next_state=s2;

s2:next_state=s3;

s3:next_state=s4;

s4:next_state=s1;

default:next_state=s1;

endcase

end

always@(posedge clk_div320k)

begin

case(state)

s1:

begin

common1=1'b1;common2=1'b0;common3=1'b0;common4=1'b0;

case(BCD_units)

4'b0000: out=7'b1000000;

4'b0001: out=7'b1111001;

4'b0010: out=7'b0100100;

4'b0011: out=7'b0110000;

4'b0100: out=7'b0011001;

4'b0101: out=7'b0010010;

4'b0110: out=7'b0000010;

4'b0111: out=7'b1111000;

4'b1000: out=7'b0000000;

4'b1001: out=7'b0010000;

endcase

end

s2:

begin

common2=1'b1;common1=1'b0;common3=1'b0;common4=1'b0;

case(BCD_tens)

4'b0000: out=7'b1000000;

4'b0001: out=7'b1111001;

4'b0010: out=7'b0100100;

4'b0011: out=7'b0110000;

4'b0100: out=7'b0011001;

4'b0101: out=7'b0010010;

4'b0110: out=7'b0000010;

4'b0111: out=7'b1111000;

4'b1000: out=7'b0000000;

4'b1001: out=7'b0010000;

endcase

end

s3:

begin

common3=1'b1;common1=1'b0;common2=1'b0;common4=1'b0;

case(BCD_hunds)

4'b00: out=7'b1000000;

4'b01: out=7'b1111001;

4'b10: out=7'b0100100;

4'b11: out=7'b0110000;

endcase

end

s4:

begin

common4=1'b1;common1=1'b0;common2=1'b0;common3=1'b0;

out=7'b1111111;

end

default: out=7'b1111111;

endcase

end

endmodule

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parallel

Altera_Forum · ‎05-18-2016

Refer to a very good article covering this - "verilog: how to instantiate a module (http://stackoverflow.com/questions/20066850/verilog-how-to-instantiate-a-module)".

You can also look at "verilog hdl syntax and semantics (http://www.asic-world.com/verilog/syntax2.html)".

Cheers,

Alex