using the LPM_ADD_SUB mega function

[Altera_Forum]

Hi, 

I developed a 4-bit SIGNED adder with a carry bit using the lpm_add_sub megafunction in VHDL in Quartus II 11.1. I'm using a DE1 board with a Cyclone II to verify the component. Here's the problem, when I add "0001" and "1111" (1 + -1) the result is 0 but the carry bit gets asserted.    Any ideas? thanks, Shawn

[Altera_Forum]

Try (+1 + -1) with 5 bits. You'll notice that a carry from fourth to fifth bit takes place. 

 In signed add, the carry bit does not indicate an overflow.

[Altera_Forum]

--- Quote Start ---  Try (+1 + -1) with 5 bits. You'll notice that a carry from fourth to fifth bit takes place.   In signed add, the carry bit does not indicate an overflow.  --- Quote End ---     Thanks for your reply. What is the difference between a signed and unsigned adder then?

[Altera_Forum]

unsigned and signed 2's complement addition/subtraction are identical and that is why 2's complement has gained popularity over say sign and magnitude.  

However, there is one anomaly here as FvM pointed at; you must ignore carry bit for signed to be correct.Moreover you must do sign extension first

[Altera_Forum]

--- Quote Start ---  unsigned and signed 2's complement addition/subtraction are identical and that is why 2's complement has gained popularity over say sign and magnitude.  However, there is one anomaly here as FvM pointed at; you must ignore carry bit for signed to be correct.Moreover you must do sign extension first  --- Quote End ---     Thanks. What is sign extension? More importantly, why do we need to designate the SIGNED attribute when building an adder in the Mega function library if the UNSIGNED adder is identical?

[Altera_Forum]

I think, the only difference between signed and unsigned add is the handling of the additional overflow output. The signed attribute of the MegaFunction is somewhat misleading.

[Altera_Forum]

example: 

"111" + "100" i.e. -1 + -4  111 100 ------  1011, discard carry bit : 011 wrong  sign extend first: 1111 1100 -------- 11011, discard carry bit 1011 (-5) correct  if I use unsigned adder for signed or unsigned values (and assume negative values are not negative) then that is ok and adder should work without further work.  if I use signed adder then the issue of carry bit has to be taken into account.  Your question why not use unsigned adder always sounds sensible to me but it could be matter of consistency to use signed adder for signed values. I am not sure if it saves much logic using unsigned adder always.

[Altera_Forum]

--- Quote Start ---  Your question why not use unsigned always sounds sensible to me but it could matter of consistency to use signed adder for signed values. I am not sure if it saves much logic using unsigned adder always.  --- Quote End ---    The gate level logic and resource usage are exactly identical for an unsigned versus signed adder. (As long as no optional overflow output is synthesized).  I don't see an essential difference for overflow behaviour between unsigned and signed adder. The basic requirement to avoid overflow is that the result must fit the existing bits. This is the case e.g. for your (-1 + -4) example, to represent -5, you simply need 4 bits. Sign extension is required to increase the word size of signed numbers before the add operation.  The available overflow detection mechanism is clearly described in the lpm_add_sub user manual. For unsigned, the carry bit indicates an overflow, for signed, an overflow bit can be generated as the XOR of carry in and carry out of the MSB.